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IP Insider Blog	By John Blyler
IP Shields but Integration Attacks In today’s litigation crazed business world, IP is the shield but deep hardware and software integration is the competitive sword. Continue reading... \| View all posts

Semiconductor IP news and trends blog with John Blyler

Latest IP

BA22 32-bit Embedded Processor
CAST

BA22 32-bit Deeply Embedded Processor
CAST

Power on Reset
NTLab

Downconvert 4:4:4 Y'CbCr to 4:2:2 Y'CbCr (ITU-R...
Digital Blocks

USB 3.0 SuperSpeed Device Controller compliant with...
Innovative Logic

PCMCIA - Host & Device Controller
Innovative Logic

Universal Flash Controller NAND/NOR/SRAM (ECC , ONFI...
Posedge Inc.

IP core based on JPEG Extended/Baseline Standard. MAX...
Shikino High-Tech

Still-image Codec IP core, based on the JPEG baseline...
Shikino High-Tech

MIPI DSI - Display Serial Interface Device Controller
Arasan Chip Systems

SD 4.0 Device IP Core
Arasan Chip Systems

OTP/eMTP: 128 Kbit NVM in 90nm Standard Logic CMOS...
Sidense

Verification IP

UFS VIP in native SystemVerilog (UVM/OVM/VMM)
Avery Design Systems

MIPI VIP in native SystemVerilog (UVM/OVM/VMM)
Avery Design Systems

Circuit Emulation Service uses SAToP/CESoPSN.Support...
ChenXiao Technologies

Burst-CDR for EPON and GPON. Based on GTX/GTH.
ChenXiao Technologies

Comprehensive memory & bus protocol verification IP -...
Cadence

Verification IP for PCI Express 3/2/1.1 + IOV based on...
Cadence

10/100/1G/10G Ethernet Monitor
Synopsys

AMBA 2.0 AHB Master
Synopsys

HDH PIF 32000 - The Verification IP for the Tensilica...
HDL Design House

MIPI HSI Verification IP in native SystemVerilog...
nSys Design Systems

HSV 900 - reusable verification solution for serial...
HDL Design House

PCI Express Gen 1-3 Verification IP
ExpertIO

Most Popular IP

4-pipe/core, 2-16 multi-core Series5XT 3D/2D/vector...
Imagination Technologies

Two Port High Speed and Ultra High Density Leakage...
Synopsys

Ethernet 10Mb - 100Gb Verification IP
ExpertIO

POR- Power on Reset (POR) for 3.0V input voltage with...
Cosmic Circuits

Interlaken Protocol IP
Open-Silicon

AES Multi-Purpose Crypto Engine
Barco Silex

MIPI HSI - High-Speed Synchronous Serial Interface...
Arasan Chip Systems

AXI Interconnect
Xilinx

Comprehensive memory & bus protocol verification IP -...
Cadence

POS-PHY Level 2 Link-layer
Altera

Highest Capacity PCI Express 3.0 Controller IP Core
Denali Software

PCMCIA - Host & Device Controller
Innovative Logic

IP Docs!

A Multi-FPGA Based Platform for emulating a 100M-transistor-scale Processor with High-speed Peripherals
(White Paper by S2C)

Exercising H.264 Video Compression IP Using Commercial FPGA Prototypes
(White Paper by S2C)

Design SoC using FPGA-based IP An FGPA-Based ESL Methodology
(White Paper by S2C)


		Mobile Phone Cameras (White Paper by Silicon Image) HDMI 1.4 (White Paper by Silicon Image) 3D and Ultra HD Video (White Paper by Silicon Image)


		Put Low-Power, Low-Overhead, High-Fidelity Digital Sound in Your Next ASIC or SOC (White Paper by Tensilica) A Processor and DSP IP Selection Checklist (White Paper by Tensilica) Everything You Wanted to Know About SOC Memory* (White Paper by Tensilica) Cut DSP Development Time – Get High Performance From C, No Assembly Required (White Paper by Tensilica)


		Vertically Integrated MIPI Solutions (White Paper by Arasan Chip Systems) Complete NAND Flash Solution: Logic, PHY and File System Software (White Paper by Arasan Chip Systems)


		Embedded Security Challenges In Automotive Designs (White Paper by Discretix) Intra-Vehicle Information Security Framework (White Paper by Discretix)

Tech Talks

FEATURED TECH TALK
When Once Is Not Enough Technology Choices for Few- and Multiple-Time Programmable Non-Volatile Memory by Craig Zajac


		RF and baseband SOC in 65 nm CMOS for Intelligent Transport Systems based on the Catena IEEE802.11x platform By Mats Carlsson (2011-11-29)


		The Challenges of Using Open Market IP In ASIC Designs By Mohit Gupta (2011-11-01)


		8051s in the Spectrum of Microcontroller Choices By Nikos Zervas (2011-10-18)


GLOBALFOUNDRIES		Concurrent Collaboration Ensures Optimized IP Development at the Leading Edge By Walter Ng (2011-08-09)


		Eliminating Test Time Hence Eliminating Test Cost (Virtually) By Yen Liu (2011-07-26) 3D IC Test is a Major Topic at SEMICON 2011 Taiwan By Yen Lieu (2011-10-11)

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Lauterbach and Beyond Semiconductors Partner for Easier System Development with BA22 Royalty-Free 32-bit Processors...

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