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IP Insider - Semiconductor IP news and trends blog with John Blyler

IP Insider
Semiconductor IP News and Trends Blog

By John Blyler

Print’s role in Semiconductor IP Design

Print content continues its steady decline in our everyday lives. But what is the real impact on semiconductor IP designs?

Few semiconductor IP designers use print exclusively for the development of their System-on-Chips (SoC). But print still plays some role a part in the creation of complex chips. But for how much longer?

Maybe not much longer, according to a number of different perspectives that emerged this week:

What role does print play in the design of your SoCs? Drop me a quick line to let me know!

 

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DDM and PLM Tools Challenge Semiconductor IP Reuse

Recent data suggests the value and shortcomings of design data management (DDM) and project lifecycle management (PLM) tools to improve IP reuse.

Last time, I focused on the potential long revenue tail of chip design afforded by the extraction, packaging and selling of semiconductor IP. IPextreme is one example of a company that enables the extraction, package and creation of licensable IP products. Websites like the GSA portal, IPestimate’s Constellation platform and Chipestimate.com can help with the distribution and potential sales – among other things.

Yet all of these companies with the exception of Chipestimate.com live outside the realm of the chip development process. Chipestimate.com provides estimation tools like InCyte Chip Estimator and Cadence Chip Planning System (CCPS) that allow designers to make IP tradeoffs in terms of power, performance and even cost. But who can help manage the actual process of chip design?

The answer lays in the world of design data management (DMM) tools, a broad category that encompasses such companies as ICManage, Cliosoft, Methodics, Numertrics, Satin Technology and others. Reaching to even higher levels of design abstraction is software-hardware tools aimed at complete system-level development. (That’s a discussion for another day – or perhaps a month of days.)

Let’s return to our level of abstraction of the chip design and semiconductor IP creation. A recent study found that one of the top factors driving the use of chip-level design management systems is “IP Reuse/Logistics Management (43%).” This data comes from the annual Global Design Management report sponsored by ICManage. Further, the year-over-year data suggests that improved IP reuse and logistics management continue to be illusive goals for most SoC developers.

 

The report also found shortcomings in existing tool offerings by noting that the most critical feature for IP reuse/logistics management is bug notification and tracing (50 %), followed closely by integrating and assembling the IP in the design (48%) and efficiently making internal IP available for reuse (47%).

Regardless of the shortcomings, any tools that can help manage the growing complexity of the chip design and IP reuse processes are welcomed in our industry.

References:

  • Collaboration Penalty Is Steep For Engineers - System-Level Design sat down to discuss chip-design productivity and quality issues with Srinath Anantharaman, president and founder of Cliosoft; Ronald Collett, president and CEO of Numetrics Management Systems; and Michel Tabusse, CEO and co-founder of Satin Technologies.
  •  The IP Blame Game - The topic of IP quality in the SoC era is difficult to define, and solutions to problems relating to IP quality, verification, and use are hard to find. Debates rage between IP users, suppliers, and EDA vendors about where the responsibility lies for making quality IP available for use and re-use in an efficient, predictable, and scalable manner.
  • EDA Extends Board Design into Manufacturing - A recent EDA and PCB acquisition represents a significant merger between the worlds of electronic and mechanical manufacturing.

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IP Adds Long Revenue Tail to Semiconductor Chips

Helping start-ups and smaller companies productize and sell their unrealized but licensable IP are the collective goals of IPextreme, the GSA and others.

Semiconductor IP touches every part of the supply chain, from foundries and chip design companies to EDA tool vendors and IP service providers. IP-Extreme is in the later space, enabling companies to extract value from the unrealized intellectual property of their chips. Achieving this goal is no small matter as System-on-Chip (SoC) complexity doubles every 18 months.

Warren Savage, President & CEO of IPextreme

The potential revenue afforded by IP can not be ignored. Warren Savage, CEO and president of IPextreme, talked about IP’s long revenue tail at the recent GlobalPress eSummit 2012.  “Semiconductor IP adds a long tail to the SoC revenue stream while also opening new markets,” explained Savage (see Figure).

IPextreme’s business model is built on enabling this long revenue stream by extracting IP from chips. This may sound like a simple process, but creating licensable IP requires a range of skills and activities, from potential IP assessment, product definition through documentation creation and product packaging. [Software readers will find a parallel in Brook’s discussion of productizing application code from, “The Mythical Man-Month.”]

Figure: The semiconductor chip revenue stream can be lengthened by extracting and selling the unique IP created during the chip design process. (Courtesy of IPextreme.)

Extracting a company’s licensable IP and turning it into a product is one thing. Delivering it and providing technical support and bug fixes to customers is another matter. That’s where IPextreme’s Xena can help by enabling IP companies to manage and distribute their IP both internally and externally to potential licensees.

How can companies further realize the long tail of IP revenue by reaching potential licensees? IPextreme is working the GSA create a website for start-ups to locate IP, related tools and services. The GSA’s Capital-Lite Resource Portal is powered by Xena to manage and use this IP, including packaging, cataloging, delivery and support.

It’s important to note that IP-Extreme is not involved in the actual design of semiconductor IP. Still, one might wonder if there was any connection between the company’s extraction technology and existing IP modeling and integration tools? I asked Savage how the GSA website compared to the Chipestimate.com or Synopsys’s TLMCentral.com sites. His response focused on the high-level TLM modeling portion of my question, noting that, according to a recent GSA survey, very few people were willing to pay for modeling of IP. (I’ll look at this issue more closely in  a future blog.)

Savage emphasized that his company was not a representative for or distributor of semiconductor IP. The company’s goal was to provide chip designers with additional revenue from the extracting and packaging of their licensable IP. To further aid in the goal, the company created its Constellations program to enable collaboration at both the marketing and engineering levels for a collection of IP companies. Membership in the program is open only to non-competing companies to encourage teamwork. Like many similar programs, this one attempts to create an environment in which select companies, “work together and share resources to promote mutual success.” (see IMEC, Minalogic, GSA)

Constellations membership currently includes Analog Bits, Certus Semiconductor, Northwest Logic, Sonics, Inc., and IPextreme itself.  The collaborative program is aimed at smaller companies that struggle to fund both marketing and technical resources for their IP products. Xena is the tool that ties all aspects of this collaboration together.

Engineers are great at creating technology that works. They are no often as good at marketing and selling the resulting products. The Constellation program addresses this shortcoming by allowing members to recommend IP to anyone with an email address and a Xena account (guests, customers and members). Prospects can follow-up on the recommendation privately with the provider. Members are rewarded with a small credit toward their Xena licenses for each referral.

Chip design companies can realize additional revenue by extracting licensable IP from their SoCs. But successfully productizing and supporting that IP requires a workable framework from companies like IPextreme and organizations like the GSA.

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jblyler‏ @Dark_Faust @globalpresspr @ipextreme Chip + #IP adds long tail on revenue stream and opens new markets.@chipestimate #semip

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Google’s Software Process Challenges Semiconductor IP

A recent FCC report blames Google’s software development process for its WiFi privacy breach. How stable is the process for semiconductor IP creation?

The findings were shocking! An FCC report concluded that a lone engineer was to blame for Google’s most controversial breach of online privacy. The report highlighted “apparently serious shortcomings in Google’s software development process.”

“These include claims from Google engineers that they were free to add code to a project without supervision if they thought they “could improve it”, a failure to follow through on a recommendation to have the privacy matter screened by one of the company’s in-house lawyers, and the pre-approval by a senior manager of a document before it was even written.” – Financial Times

This is simply shocking! How could these horrendous missteps have happened? Perhaps to meet deadlines, improve product performances or the morale of the developers?

Certainly these shortcomings never happen at other software development companies! After all, what manager would approve changing the code to improve performance? (Answer: Almost any.) Or what engineer or manager wouldn’t enjoy meeting with legal beagles to explain any technical issue? (Answer: Almost all.)  And what manager hasn’t pre-approved some paperwork to get a project going or back on track? (Answer: The great majority.) In case of documentation, the FCC report doesn’t indicate if the document was a software specification, user guide or product brochure.

My somewhat sarcastic point is that all of these shortcomings in Google’s software development process are common practices – sometimes even best practices. Anyone who has led a team of software developers in the real world – as I have – can attest to the occasional transgression to meet deadlines, stay on budget, improve the product or just get the job done.

Even the most serious allegation in the FCC report seems inconclusive. The search company originally blamed the privacy breach on a lone engineer who intended to write software to collect WiFi network data, not personal information. The validity of that claim should be easy enough to discern by looking at the code. A peer review of the software would quickly confirm the developer’s guilt or innocence.

Blaming the software development process is a tried-and-true way to divert responsibility from management. Neither the FCC report nor Google’s responses provide much insight. One is tempted to ask how Google measures the maturity of their internal software process. Do they use a standard Capability Maturity Model Integration (CMMI) approach or something similar? Searching Google for the answer is frustrating at best. Try it.

Characteristics of the Capability Maturity Model "best practices" for software development.

Some readers may wonder what all of this has to do with semiconductor IP development. Software development challenges are headaches faced by all engineers, programmers and managers – from applications and middleware down through firmware and even – gasp! – chip specific RTL. Have you ever wonder if a method exists to evaluate the software development process of semiconductor IP? Not the verification of IP functionality, but the validation of the development process itself?

Warren Savage, CEO of IP-Extreme, shared insights into this question and others during an interview at the recent GlobalPress eSummit. Look for Savage’s comments in my next blog.

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Free IP or the Soprano Model?

John Blyler and Sean OKane mix it up when talking about open source semiconductor IP, Minalogic, Greensocs and a potential buyer for MIPS.

Although last month’s DesignWest show focused on embedded technologies, a few attending companies did talk about matters of interest to the semiconductor intellectual property (IP) market. John Blyler, author of the “IP Insider blog on ChipEstimate.com, talked with one of the companies – Minalogic, a technology cluster center based in Grenoble, France.

From there, the semiconductor IP discussion took an unexpected turn into the world of open source hardware and software, promoting a question about open source IP. Sean O’Kane, producer/host ChipEstimate.TV, proposed a “Soprano” model for IP – “You give me a little IP, and then when we make the chip, you can give me a little bit back.” That was an offer that few could refuse.

The talk ended with speculation about a potential buy for MIPS.

Free IP? John Blyler and Sean OKane talk on ChipEstimate.com

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High-Level Synthesis without IP Hassels?

Start-up Algotochip offers illusive C-to-chip generation in record time, but raises questions of automation vs. customization and IP ownership.

Algotochip emerged from stealth mode this week at the Globalpress Electronics Summit 2012 in Santa Cruz, CA. The company announced delivery of their silicon solution based on MimoOn’s LTE reference chain, a wireless industry platform for Software Defined Radio (SDR)

The “Blue-Box” claims to transforms C-code algorithms into complete RTL-based silicon chip implementations.

Algotochip – short for Algorithm to chip – claims to create production-ready System-on-Chip (SoC) designs from C-code algorithms. Creating low-level, hardware RTL-code from high-level, software C-code is a long sought goal of the electronic design automation (EDA) industry. What makes Algotochip’s position unique is the claim to deliver silicon hardware in as little as 8 to 16 weeks – instead of the more typical months or years. How is this possible?

Satish Padmanabhan, CTO, claims the secret to the companies fast turnaround time lies in the hardware-software partitioning process.

“Designers can not define a complete system in C or System-C since there is no cycle-based information in C-code,” explained Padmanabhan. “One must take the C-code and then decide what needs to run in programmable (software) and non-programmable (hardware) implementations.”

Typical chip designs start with some amount of existing RTL code. But to do high-level synthesize, engineers must start at the architectural levels using C algorithmic code. At this higher level of abstraction, functions have not yet been apportioned to hardware and software implementations. This is where Algotochip claims to help, by solving the difficult challenges of hardware and software tradeoff decisions.

An example of an algorithmic equation – Kalman filter used in wireless designs – as implement in MATLAB before conversion into C-code.

According to the company, customers need only submit their system specification, C-code with test vectors. The company will use these inputs to partition a solution in hardware (SoC, S-ASIC or FPGA) and software (compiler, simulator) and firmware.

How does this approach compare to other design service businesses like eSilicon and Open Silicon? According to the Algotochip’s Padmanabhan, time is the big differentiator as measured in weeks (8 to 16 weeks typically) rather than months or years to tape out.

In terms of semiconductor intellectual property (IP), Algotochip will incorporate third-party IP or will create customer specific IP from proprietary C-code algorithms. Interestingly, the company claims that their customers will retain all intellectual property rights pertaining to the finished design. Some critics doubt this claim as IP makes up a significant portion of revenue for most chip design service companies.

Another area of concern is whether Algotochip SoCs will really be as power-efficient as those that use traditionally longer-time frame development tools and processes. The short development process – 8 to 16 weeks – suggests to some that the Algotochip offers a more customized rather than completely automated approach for C-to-RTL silicon creation.

Time will tell if Algotochip’s design services can really beat traditional C-to-Chip methods for timely and power-sensitive SoC development. Related issues such as IP ownership should also become clearer after the company enjoys further customer engagements.

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IP Tech Bits – Bold Fiction, Wireless Power, Games, Unpatentable Processes and FPGA in Broadcast

Here’s a short list of recent news stories that show the reach of semiconductor intellectual property (IP) across many industries.

1. Why We Need Big, Bold Science Fiction

Are you looking for a way to inspire the next generation of science and engineering students? This Popular Mechanics story reminds us why we need inspiring science fiction, not just tales of dystopias like the Hunger Games. Unfortunately, the author sees space as the primary background for this big, bold tales while neglecting the realms of nano- and quantum-technologies. Still, it is a good read.

2. Wireless power system for mobile electronics

Scientists at Fraunhofer Institute for Ceramic Technologies and Systems IKTS in Hermsdorf have succeeded in the wireless transmission of power to electronics around the body. Several months ago, I reported on Intel’s and TI’s wireless power charging subsystems. Any such technology will require additional analog and power IP in the support chips.

3. Should Smart People Care About Video Games?

At first glance, there seems to be no direct correlation between this article and semiconductor IP technology until you think about the future trend in games for 3D graphics, augmented reality and more sensory experiences. To realize these trends, designers will need to add much more analog and graphic IP from vendors like Imagination Technology, ARM, AMD, nVidia and others.

4. Natural Processes are Unpatentable – Finally

The Supreme Court ruled that natural processes are not patentable. This decision was aimed at drug manufactures, but might have implications to new smart sensor algorithms that are flourishing in the mobile chip (e.g., gaming) and embedded systems industries.

5. FPGA IP Helps Kill Cable

The British Broadcasting Corporation (BBC) has designed a prototype camera-back device that enables very high-speed, broadcast grade video transmissions over internet-protocol based networks. The prototype replaces a mess of other cable interfaces with a single network cable (fiber or Cat6) by using a Xilinx FPGA – and undoubtedly a lot of interface IP. Check out the number of connections on this box!

Who would have known that the BBC has an R&D branch that – among many other things – helps technology transfer of patents and intellectual property to other industries.

 

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MIPS Sale Raises Chinese IP Issues

Speculation about China’s acquisition of MIPS processor IP raises familiar questions about the value of chip development without patent enforcement.

MIPS, the once prominent IP processor company, has caught the attention of investors. According to a Bloomberg report, the company recently hired Goldman Sachs Group Inc. to help find and negotiate with potential suitors. Earlier this year, MIPS Chief Executive Officer Sandeep Vij told analysts that the company was pursuing “several paths towards monetization” of its patent portfolio.

Sandeep Vij, President and Chief Executive Officer

According to Bloomberg, ThinkEquity’s De Silva said that Broadcom Corp., MIPS’s biggest customer, and Qualcomm Inc. may consider purchasing the company to gain further processor offerings. Other potential buyers include licensees such as Broadcom and Texas Instruments.

Some have even speculated that chip design tool vendor Synopsys might buy MIPS. In 2009, Synopsys acquired the analog portion of MIPS. The remaining IP processor portion of MIPS might offer customers other choices to Synopsys’s ARC processor (via Viragelogic) line of cores.

A more speculative conjecture is that that the Chinese would be interested in legitimizing their already heavy use of the MIPS architecture. Readers might recall that, in 2005, the Godson processing architecture so closely mirrored that of MIPS that even the analyst firm In-Stat wondered about serious IP and patent infringement issues.

In a country where product production trumps any concern for patent infringement, it seems strange to even speculate on the acquisition of an IP company. Further, it is doubtful that existing MIPS licensees in the US would want their contracts handled by a country with such questionable IP enforcement or support.

All this speculation does invite re-examination of the value of IP-based US technology companies designing or manufacturing complex integrated circuits in China. Years ago, I raised this issue with Chris Rowen, then CEO of Tensilica – a company that has successfully provided extensible IP processor cores to some of the same markets as MIPS. Rowen addressed the issue in a article titled: Hope and Fear: Doing Intellectual-Property Business in China

Chris Rowen, Ph.D., Founder, Chief Technology Officer

Rowen explained that the only thing worse than having your company’s IP stolen is to have people steal your competitor’s IP. The basis for this reasoning was that the more people who used a particular processor platform, the more likely it is to become a defacto standard. “….(Processor companies) are biased toward wider proliferation in rapidly emerging markets like China,” explained Rowen.

The struggles that MIPS has experienced in China suggest that a critical mass of IP must be used-stolen before it becomes a defacto standard. Further, won’t the process of becoming a defecto standard drive down the price of the legitimate IP?

But acquiring processor IP is only one part of the challenge in building ICs. The second hurtle comes in chip manufacturing. Current Chinese foundry technology seems to lag about two generations behind the developed nations. Ironically, the lack of IP enforcement is one of the reasons why few major players want to build the lowest node chip fabs in China.

Although it seems doubtful that China is interested in acquiring MIPS IP business, the potential sale does re-ignite questions about the value proportion for IP companies on the Asian continent.

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Free Hardware and Software but not IP

Will the success of the open source movement in software and even hardware cause changes in silicon IP business models?

After posting the story on Minalogic – the French technology centered in Grenoble, I receive a note from an electronic engineer in the area. In his missive, Henri stressed the importance of a common hardware and software platform to enable the technical innovation and exchange that was the goal of clusters like Minalogic. In particular, he emphasized the need for open hardware, recommending the Open Source Hardware (OSHW) movement  

Dr. Gary Ray

The challenges in creating open hardware platforms in the chip and (to a lesser extent) the embedded board markets have been around for some time. They have also been a topic of personal interest. Dr. Gary Ray, a college friend of mine, once wrote a series of articles discussing the challenges of open hardware design starting with this one: Reproducible Research – Studies in Open Source Hardware Design  

 Although a few years old, the chip and embedded open source hardware tools mentioned in my overview article are still applicable – see, “Open Source Hardware and EDA tools”  

Free and open source hardware-software tools have enabled innovation in the embedded space and – to a lesser extent – the world of chip design. But what about free intellectual property (IP)? Here’s where the story gets “interesting.” Giving away intellectual property is like giving away one’s gold.

Building Blocks for Tool Independent ESL SystemC from GreenSocs.com

Mark Burton, founder of the open source SystemC community and initiative called GreenSoCs, once put it this way:

“For the silicon industry, there is a tension here, because this industry deals with extremely high value Intellectual Property (IP). The silicon design itself represents the “crown jewels” for a silicon company. These designs are traded between companies for large sums, under relatively complex licensing terms. Thus, for this industry, the concept of “Free” or “Open” IP is not easy to mix with their own high value IP.”

 From the silicon design industry’s viewpoint, the main obstacles are twofold, explained Burton. First, the design itself needs to be licensed in such a way as to enable “free” access. Secondly, the means by which the design is “accessed” must also be “free”. This means that both the IP and the tools must be free.

Free IP and tools have been the norm in the world of FPGA designs, although that model is changing as FPGA approach ASIC/ASSP in design complexity.

Software has long been the shining model for free IP and tools with such examples as the GNU ‘C’ compiler. In the silicon world, SystemC has come the closest to a free tool offering.

The idea of free silicon IP is nothing new. Back in 1999, Artisan (now ARM) offered free semiconductor IP design libraries to silicon developers within its large user community. The company’s reason for this free giveaway as to simplify IP integration, particularly for Artisan-based system-on-chip (SoC) designs.

The “free IP” business model meant that Artisan would forgo the typical up-front licensing fees and instead receive royalties from their foundry (then TSMC) for each chip made with its design cells. Eventually, the approach led to the collapse of many smaller cell library providers – like Aspec Technology. Larger and more successful vendors like ARM survived by making similar foundry-specific versions of their design cells.

But is free IP really “free?” Not if you take the big picture view beyond the initial IP licensing fee, reasons Kurt Shuler, VP of Marketing at Arteris. He backs up his argument – at least for the Network-on-Chip IP market space – with recent data from the semiconductor market research firm Objective Analysis. The study confirmed that the economic benefits of using NoC interconnect IP were more than 10x the license price for the IP. Further, the report claims that the benefits include a much higher ROI than internally developed or “free/bundled” interconnect IP.   

The continuing success of the open source movement in software and even hardware may cause changes in the silicon IP business models. Still, the real challenge will be how to keep innovation alive when the cost for creating new designs returns no financial benefit to the IP creator.

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Reference: System-on-a-Chip Integration in the Semiconductor Industry: Industry Structure and Firm Strategies, by Greg Linden and Deepak Somaya, October 20, 2000



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Verification IP Faces Hardware and Software System Challenges

Design and verification IP must evolve to enable the full integration of hardware and software subsystems.

Verification intellectual property (VIP) has benefited from both EDA and IP growth. As Ed Sperling reported recently on System-Level Design, the highest growth reported (for 4Q2011 in EDA) was in physical design and verification, which grew 30% year over year to $392.4 million. IP revenue also grew 13.4% to $432.2 million. The growth of both EDA verification tools and IP in general bodes well for verification IP.  

What has spurred this growth? One reason is that System-on-Chip (SoC) designers rely increasingly on IP reuse – especially interface IP – to meet both increasing design complexity and shorter time-to-market product cycles. But hardware IP must be verified at the component level and then verified once again after integration to the overall system, which drives the need for additional VIP.

Another factor in verification IP growth is the increasing use of design IP over stand alone chips to increase functionality of the SoC block. This is especially true for interface and bus IP, which is tightly integrated with corresponding software protocol IP like device drivers. Thus, verification is needed for both the hardware and related software IP to form a reliable interface subsystem. This trend is a natural evolution of component IP to subsystem blocks and even higher-level system IP.

When asked how this move toward a system context will affect the growth of intellectual property, Neil Hand, marketing group director at Cadence, put it this way: “And once that (software and firmware IP issues) gets solved, the next thing is how you build that (IP) into the system level models and supply chain models … But we’re at such a low level on the IP side that there’s a lot of integration that has to happen.”  

Indeed, a great deal of integration issue lie ahead as component IP evolves into subsystems consisting of both hardware and software firmware. Fortunately, these challenges are being resolved, thanks in part to the hardware “awareness” of firmware, device driver software and even operating systems.

The challenge really begins with the incorporation of system-level, hardware “unaware” software applications as in the end-user consumer space. Merging these two great intellectual property domains – hardware and software application – will not be easy. Complicating matters is that hardware and software engineers speak a different language while using the same words.

Add to this enormous challenge the fact that user experience will drive many future designs. This means that a real-time, end-user feedback loop will need to be developed and maintained through the SoC engineering development process. Software application engineers are familiar with this approach. Silicon hardware engineers are less so. 

Verification remains the one constant throughout all of these hardware-software evolutionary integrations. But verification will need to change and adjust to the coming user driven development methodology. Several pundits have acknowledged the need for VIP changes, though each from a differing point of view. For example, Faisal Haque, Sr. Director of Engineering at Qualcomm, stated that VIP architecture had to be revisited and redesigned for scalability and customization. “We must stop adding code to already bloated VIP and go back to basics,” said Haque. (see, “Verification Complexity Driving Innovation in VIP”)  

Design and verification IP must evolve to enable the full integration of hardware and software subsystems.

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