Recent Executive Actions by the White House add some tools for victims of trolling, but Congress must act for real reform to occur.
Earlier this week, I received an email concerning three new executive orders designed to fight patent law abuse. As the name suggested, these orders came from the Office of President Obama. According to this email, the goal of these orders was to protect innovators from expensive patent infringement suits initiated by patent trolls.
Most lawyers will agree that being on the defense side of a patent litigation is usually the most profitable position. It’s even better when you’re defending a deep-pocketed major company.
But what is behind these executive orders? Will they really have an impact on patent trolling.
According to Jonathan Kaplan, IP semiconductor lawyer, one has to be very careful to distinguish between the terms “Executive Order,” “Executive Memorandum,” and “Executive Action”:
A quick check of the White House’s Fact Sheet indicates that the earlier mentioned executive orders were not really orders at all, but rather Executive Actions. Here’s a listing of these informal proposals made by the President:
In addition to these three Executive Actions, the fact sheet includes an online toolkit, “aimed at empowering consumers with answers to common questions, information about patent suites and details about specific patents.” For example – as reported by Gigaom – one source of information provided by the U.S Patent office will be a link to a Lex Machina tool that allows troll victims to compare demand letters, i.e., those missives that trolls send out to untold number of businesses.
Will these Executive Actions really have a significant impact on patent trolls? It seems doubtful.
“The real action on this issue is taking place right now within the Senate, which took up the “patent troll” issue after the House passed the Goodlatte bill,” explained Kaplan (seePart I, Part II, and Part III).. It seems that Congress must act before anything significant actions can occur.
As the EDA world shifts gears toward software-driven SoC design, the US Supreme Court is deciding if software is even a patentable process or entity.
The creation of today’s complex system-on-chip (SoC) devices relies solely on the use of EDA tools and methodologies. Over the past few years, the EDA community has faced supply chain challenges that forced it to embrace software in a big way. This challenge goes beyond the software of EDA tools to include device drives, interface stacks to even end-user applications.
Today, the big three EDA companies provide a variety of software offerings to complement their tool products. For example, Cadence is a major provider of semiconductor-related intellectual property (IP) software. In 2013 alone it acquired Tensilica (confirmable processor IP) as well as Evatronix (controller IP) and Cosmic Circuits (analog and mixed-signal IP). These acquisitions build upon the company’s existing verification IP portfolio.
Mentor Graphics has been involved with operating system (OS) and application system software for many years in its embedded business. Yesterday, Synopsys announced the acquisition of Coverity, a San Francisco based software company that provides enterprise-level static code analysis tools and security testing for C, C++, Java and C#.
The trend for EDA companies to provide hardware, software and complete systems represents a move back to vertically integrated electronics design, notes Chris Rowen, Founder of Tensilica. “It’s something we haven’t seen since the 1970s and 1980s.”
Examples of the vertical trend in electronic design can be found at Google, Apple, Facebook and Amazon. Each of these companies, in differing degrees, is developing their own silicon in addition to software and entire systems.
The challenge is that hardware and software are not mutually exclusive implementations. And both are growing in complexity. Today systems must not only simulate hardware but also simulate the application running on the software. “Hardware by itself cannot be deemed correct. Software-driven SoC design will be a big theme amid this roiling change,” cautions Rowen.
The technical professionals in the semiconductor world understand the symbiotic relationship between hardware and software. Unfortunately, the legal community seems to have a different view.
Is Software Patentable?
Jonathan Kaplan, a respected IP lawyer in the semiconductor space, has been writing about the issue of software patentability in a recent series of blogs (see Part I, Part II, and Part III). Kaplan explains that the question of patentability is governed by § 101 of the US patent laws. This is a fairly broad law which is now being tested to the limits. Below is a brief summary of Kaplan’s key points.
The ramification of unpatentable software would be difficult to fully envision. Kaplan and I will cover more on this issue in the coming months.
How do recent acquisitions in the high-level synthesis (HLS) market affect methodologies like behavioral synthesis, platform and model-driven designs?
Recently, I wrote about changes in the high-level synthesis (HLS) market due to Cadence’s acquisition of Forte Design. While talking with various experts, I began to wonder how developments in the high level synthesis market might affect other semiconductor IP dependent processes like behavioral ESL, platform-based design and even model-driven design. What follows are insights on these questions from Nikolaos Kavvadias, CEO of Ajax Compilers. – JB
Blyler: Behavioral ESL tools create models for trade-off analysis. How do these tools relate to higher-level modeling tools/techniques like platform-based design or EDA/CAD model-driven design?
Kavvadias: According to the ITRS 2011-2012 roadmap, it is expected within 8-10 years to have 100% accurate early performance prediction tools which are mandatory for efficient trade-off analysis. This implies an outlook and expectation for platform-based design predominance against EDA model-driven design. Some acquisitions bring EDA tools inside the ecosystem and make them less visible and accessible. The companies with the strongest IP portfolios will put their money on the prevalence of IP-based platform design.
Blyler: What is the difference between platform based design and model-driven design? Aren’t both depended upon IP?
Kavvadias: In my view, platform-based design is defined by the presence of an OS-running processor, which also defines the main interconnect used (an example is the ARM/AMBA combination), plus mostly reusable IP and a stable tool chain.
In model-driven design, both hardware, software and tool chain are extracted based on MDE principles. This could be UML for the software layers and an increasing use of hardware Architecture Description Language (ADL) for processor, component design and tool chain development.
Blyler: How do these two approaches compare to Cadence’s new “System Design Enablement” approach?
Kavvadias: I think Cadence with their System Design Enablement approach incorporate verification and rapid prototyping aspects into the platform, albeit the platform in this case is defined in a more relaxed form. The platforms here also stand-in as specializations of their flow with certain fixed points to allow faster design and verification turnarounds.
The high-level synthesis market for ASIC and FPGA designs just got more interesting with Cadence’s acquisition of Forte. But what about the models and IP?
The relatively quiet high-level synthesis (HLS) community was awoken this week by news of Cadence’s intention to acquire Forte Design. Does this acquisition portent changes on the modeling and intellectual property (IP) integration front?
I’m exploring these questions with industry experts but that story is not yet complete. What is known is that high-level synthesis (HLS) is vital for ASIC and FGPA designers are they interface with the system-on-chip (SoC) system architects. These HLS tools follow the electronic system-level (ESL) methodology to provide the high-level power and performance trade-offs necessary to move a design from the behavioral to partitioned architectural levels. To be specific, HLS transforms behavioral C++ models into untimed Verilog RTL.
But as Gary Smith warns, ESL is not a software process as the end result is the creation of hardware. “Do not consider behavioral ESL design as software, it’s modeling.” That is why Smith’s big message to the EDA tool companies at last year’s DAC was, “give away the (ESL) tools if you must, but sell the models.”
It is the models and the related IP that make the Forte acquisition of such interest. How will Cadence work these assets from Forte into both it’s existing HLS “C-to-Silicon” tool as well as Cadence’s own EDA360 vision for SoCs development and beyond. For now, though, the acquisition seems to signify an important move for the HLS community. Further, Smith sees it as, “a good sign of Cadence’s renewed presence in the EDA market.”
A quick curation of past interviews highlights model creation, open system IP, reproducible designs, iTunes EDA and security approaches from industry experts.
Last week, I spoke to the Seattle chapters of both the Society of Automotive Engineers (SAE) and International Council on System Engineering (INCOSE). The presentation gave an overview of hardware and software integration and co-verification at the chip, board and vehicle network domain. The best way to verify and integrate at each domain was through the use of model-driven design (MDD) techniques.
At the end of the presentation, two questions were asked:
These were great questions! To address them, I pulled from past interviews, articles and videos. What is listed below is the best of that curation. — JB
DAC Panel Explores IP Theft in Global Markets – Here are the essential opening remarks from the DAC Pavilion presentation on the development and integration of IP, delivered by Chipestimate’s General Manager, Adam Traidman. In Part II, noted panelists from GlobalFoundries, IDT and the legal community will explore the technical, business, and legal challenges of cross-regional IP sourcing and associated worldwide business integrity challenges.
Security Plays Key Role in IP-based Design Growth – What can be done to reduce the success of reverse-engineering and cloning techniques? One of the best ways to protect any data — be it related to application-software or hardware-design IP — is through the use of sophisticated encryption techniques.
IP Smoke Testing, PSI5 Sensors, and Security Tagging — The thing that has been missing (from IP security) is what to do about soft IP. (Editor’s Note: Soft IP is synthesizable in a high-level language like RTL, C++, Verilog, or VHDL.) Watermarking the code is a common approach for tracking soft IP and one that we use at IP Extreme. I’ve been working with Kathy Werner, who heads a committee on soft-IP tagging. She has worked with IP at Freescale and then Accellera. Her committee is incorporating many of the same conventions into soft IP that proved successful in hard IP. The goal is that these soft-IP security mechanisms will work throughout the EDA-tool design flow to be propagated downward into the GDSII. In other words, the high-level soft-IP tags could be detected at the GDS level.” – Warren Savage, President & CEO of IP-Extreme
II. Models and Modeling
IP Characterization Moves from The Backroom — “People are getting IP from multiple sources. This presents many challenges, chief of which is how the IP models were created. Since there are no standards for IP model creation, designers use many ad hoc methods and tools that don’t do a complete job.” – Jim McCanny, CEO of Altos Design Automation
Free Hardware and Software but not IP – “For the silicon industry, there is a tension here, because this industry deals with extremely high value Intellectual Property (IP). The silicon design itself represents the “crown jewels” for a silicon company. These designs are traded between companies for large sums, under relatively complex licensing terms. Thus, for this industry, the concept of “Free” or “Open” IP is not easy to mix with their own high value IP.” – Mark Burton, founder of the open source SystemC community and initiative called GreenSoCs,
Mysteries of Reproducible Chip Design – Let’s examine a more controversial and global viewpoint. Imagine a world in which IC design houses described their proudest creations in public documents that tell the world every detail. Any reader could download the GDSII file, complete netlist, Verilog source, block diagrams, and every parameter needed to recreate the chip being described. Sounds far-fetched, doesn’t it? This might seem ridiculous in 2007. But consider the world of computers and software 25 years ago… – Dr. Gary Ray
iTunes Business Model for EDA IP – How do third-party IP vendors in the ASIC and embedded spaces compete with the “free” IP provided by FPGA-companies? System-Level Design explored this question with OptNgn Software, a start-up company.
While admittedly long, this list captures the diversity of our coverage – from IP trends to the Rule of Nine, lost innocence, Indy racing, sci-fi, and the Acorn.
It’s time again for my yearly retrospective look at all of the stories that I’ve covered on “IP Insider.” This breadth of coverage is why I enjoy working with the folks at Chipestimate.com (i.e., they allow my carte-blanche selection of topics!). Their only request is that the subject matter bares some connection to the world of semiconductor IP. Fair enough!
Below are my two favorite blogs from each month in 2013 based upon the quirkiness of the topic – from the extreme to the mundane. There’s always something of interest to report in even the most unassuming of stories. Happy Holidays! -JB
During my recent coverage of the International Electronics Forum in Dublin, Ireland, I interviewed Tony King-Smith from Imagination Technologies. We talked about a holistic end-user approach to IP development; verticalization by non-Tier-1 companies for chip design; and creating actual consumer products (like Pure Radio).
Creating a working synaptic-transistor device should help with the modeling of neurons in the Human Brain Project. But would the IP be open to all?
Harvard scientists have created a transistor that mimics the behavior of a neural synapse, notes a recent article in R&D. This new device modulates the flow of information in a circuit while physically adapting to changing signals. A system that integrates millions of synaptic transistors could open the door to a new area of parallel computing – beyond today’s semiconductor-based systems. But what do synaptic devices modeled after semiconductor-transistor technology mean for efforts to synthesize human thought?
Last month, Karlheinz Meier, Chair of the Experimental Physics department at Heidelberg University, presented at Malcolm Penn’s IEF event in Dublin, Ireland. Professor Meier shared the latest highlights of the Human Brain Project (HBP), which is developing a novel computing architecture for synthesizing thought.
The Blue Brain Project (BBP), part of the Human Brain project, is attempting to reconstruct the brain piece by piece to build a virtual brain in a supercomputer. In practice, the BBP is reverse engineering the mammalian brain down to the molecular level. At that level, cells in the nervous system (known as neurons) serve as the basic building blocks. Neurons are different from other cells in that they can transmit information throughout the body via synaptic interfaces.
Neurons are a key element of both the Harvard synaptic-transistor and brain-simulation projects. Understanding the device characteristics of these unique transistors should lead to greater accuracy of neural device modeling in the Human Brain Project. This is analogous to improved transistors leading to better device modeling in analog semiconductor design.
One is tempted to ask if a neuron is the equivalent of a semiconductor transistor. It’s more accurate to define a neuron or neural cell as an “entity” on the silicon substrate. I defer this discussion for another blog. (See “A Working Transistor Built Out Of DNA Within A Living Cell“)
Creating a working synaptic-transistor device that ultimately improves neuron models of the human brain seems analogous to transistor creation and device modeling in the semiconductor world. One big challenge in the latter is the openness of the data used to create the model. Will the biological designers follow an intellectual-property (IP) model similar to that of the semiconductor world?
I asked Professor Meier about the IP and access issues associated with the Human Brain Project in terms of aggregating the neuroscience brain data, which is a prerequisite for modeling and simulation. Would that data be open to all? Would there be any IP issues?
In response, Professor Meier directed me to Paul Allen’s mouse brain project. Last year, software billionaire Allen pledged $300 million to establish a series of “brain observatories” in Seattle. The goal of those observatories was to map and manipulate the brain of a mouse as the first step in understanding higher-order mammalian brains.
According to Meier, data from Allen’s brain observatories are totally open. “We would make (our Human Brain Project) data open too,” said Meier. “Intellectual property becomes important when developing a circuit. But for the biological data (from the HBP), there is no secret data of which I’m aware.”