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The growth of semiconductor IP brings challenges for subsystem verification, integration, security, and the addition of sensor standards. Can Savage clear the smoke?

Warren Savage, marathon runner and President & CEO of IP-Extreme, talks about the trends, misconception, and dangers resulting from the increasing popularity of semiconductor intellectual property (IP). What follows is the first portion of a two-part story.

Blyler: Let’s start by talking about trends in IP for field-programmable-gate-array (FPGA) and application-specific-integrated-circuit (ASIC) systems-on-a-chip (SoCs). What’s new?

Savage: If you look at global macro trends, you’ll see an increased amount of customization. For example, the iPhone can be customized “six ways to Sunday.” I’m starting to see something similar in the semiconductor space, where companies are differentiating themselves through IP and putting it together in different ways. Some guys – the Broadcoms and Qualcomms of the world – can do huge quantities of SoCs. But many mid- and lower-tier guys are doing more customized types of products that appeal to a certain niche market. [Editor’s Note: Makimoto’s Wave remains in its customization cycle.]

If the volumes are low enough, an FPGA with the right IP could offer a big differentiation from an off-the-shelf (ASIC) SoC. I’m seeing more of that trend and it gets stronger every year.

Blyler: The numbers are showing that IP continues to be a larger share of the revenue. How about subsystem IP? Is it starting to take off – perhaps in the vertical integration of certain types of IP?

Savage: One of the artifacts of the downturn from several years ago is that fewer engineers must do more increasingly complex things. We are seeing people buy more of our subsystem IP that includes the processors, bus infrastructure, and peripherals needed to run a real-time operating system (RTOS). People want to buy the whole thing and start with a working platform, then add their IP around that platform.

Blyler: Won’t the move toward subsystem IP lead to more verification and integration issues? Does the entire subsystem then come with a suite of tests or do you need to test each IP block individually?

Savage: The expectation is that the subsystems are fully verified and come to the designer as a black box. Typically, people don’t re-verify things of that complexity; it is too much. Plus, it has already been verified at the subsystem level by the IP provider. What the IP provider supplies is some type of integration-level test so the designer can – for lack of a better word – run a “smoke test” to ensure that the subsystem is installed properly and fundamentally working. In processor-based designs, it means you can run software like a “hello world” test that verifies all of the memory, interface, and peripheral connections.

Not a lot of extra verification tests come along with the IP. After all, the IP is expected to be used as a black box.

Blyler: With the rise of sensors in our increasingly connected world, I would expect to see more sensor-related IP. Is that the case? Or is it a microelectromechanical-systems (MEMS) technology and fabrication issue?

Savage: One of our major customers is a provider of automotive sensors. They use MEMS technology for sensors, accelerometers, etc. – as part of their products. But these MEMS chips and sensors still need to be connected into an SoC. That’s why we’re seeing interest in the Peripheral Sensor Interface 5 (PSI5) standard, which is a specific interface dedicated to automotive sensor applications. PSI5 is kind of an upgrade to the Local Interconnect Network (LIN) standard.

Here is an overview of hardware interfaces (courtesy of Vector).

For background, there’s a hierarchy of automotive interface standards. At the low end of complexity is LIN, which is typically used to control the mirrors on a car via a driver-side toggle switch. Next comes the controller-area-network (CAN) bus interface, which has a lot more bandwidth for moving data around. CAN is used for suspension, airbags, etc.

Lastly, FlexRay is a true vehicle network for real-time apps. Eventually, it will give way to a drive-by-wire or steer-by-wire implementation.

Blyler: What’s new on the security front for semiconductor IP?

Savage: On the commercial side, I’m seeing less and less concern about security. But there are some developments that will be important. For some time now, there has been an IEEE standard on hard IP tagging that allows you to track cores at the GDS level. (Editor’s Note: Hard IP is offered in a GDSII format and optimized for a specific foundry process.)

The thing that has been missing is what to do about soft IP. (Editor’s Note: Soft IP is synthesizable in a high-level language like RTL, C++, Verilog, or VHDL.) Watermarking the code is a common approach for tracking soft IP and one that we use at IP Extreme. I’ve been working with Kathy Werner, who heads a committee on soft-IP tagging. She has worked with IP at Freescale and then Accellera. Her committee is incorporating many of the same conventions into soft IP that proved successful in hard IP. The goal is that these soft-IP security mechanisms will work throughout the EDA-tool design flow to be propagated downward into the GDSII. In other words, the high-level soft-IP tags could be detected at the GDS level.

Related Stories:

• IP Adds Long Revenue Tail to Semiconductor Chips
• Trends in Subsystem Semiconductor IP
• IP Tagging Gains Renewed Interest