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IEEE-IMS was Busy and Productive for RF and MW Developers
Highlights from the major IEEE RF and Microwave show include the purported death of GaAs, non-CMOS stacked die, women engineers, and microapps.
Known as the leading technology showcase for RF and microwave theory and design, this year’s IEEE MTT-S International Microwave Symposium (IMS) enjoyed unusually sunny weather in this year’s host city of Seattle, WA.
Reports suggest that attendance was healthy for a region that’s not known for its abundance of MW and RF engineers. Academics presented their latest works to a focused audience. And most attendees, partners, and exhibitors seemed pleased with the event.
One of the panel sessions had the catchy title, “The Death of GaAs.” This technology has been essential in the rapid growth of wireless communications. But silicon-based technologies like RF CMOS (think Qualcomm front ends), SiGe, and silicon-on-insulator (SoI) are challenging the GaAs domain in the high-volume mobile market segment. Further, technologies like GaN are seeing wider deployment in aerospace and defense applications. Products using these alternative technologies pose increasing challenges to the GaAs device industry. The panel speculated on the future of the GaAs market, concluding that it still has a role to play.
This panel was covered in Patrick Hindle’s blog and follow-on discussion in the LinkedIn RF-Microwave Community. He made two points in his write-up that caught my attention. The first point concerned SoI and Silicon-on-Sapphire (SOS) switches, which – thanks to their lower cost – seemed to be replacing GaAs in many designs. Hindle clarified that trend by noting that, “SoI switches are widely replacing GaAs switches in handsets, while GaAs continues to do well in higher-performance applications” (see “CMOS and SoI Invade RF Front End“).
Another interesting point from Hindle was inspired by a DARPA presentation about combining InP HBT, GaN, and MEMS on the same platform. To me, the project seems like another implementation of 3D stacked-die technology, sans the more typical processor and memory dies. If that is true, this would be an interesting twist on the more common silicon-based CMOS stacking trends.
On the exhibitor side of the show, AWR’s VP of Marketing, Sherry Hess, hosted the gifting of AWR software to the winners of the company’s SDR and PA student design competitions. She noted that the Microwave Application Seminars (MicroApps) – 20 minute technical presentations given by the exhibitors – were well attended. “We had 30+ in the audience for each of AWR’s talks,” she said, where topics ranged from simulation to design methodologies.
One of the big events on the social side of the show was the Women in Microwaves reception, held in Seattle’s iconic Space Needle. As co-chair of the IEEE’s Women in Engineering (WIE) group and longtime advocate for women in engineering, Hess was pleased to see that the reception – collocated with the HAM Radio gathering – topped 300 in attendance. According to Hess, another big social event was the annual AWR appreciation party, which had record attendance of nearly 1000 people.
All in all, IMS 2013 seemed to have been reasonably well attended with lively technology discussions and great social events in the evening. As Hess said, it was a busy, productive, and exhausting show, but the time was well spent!
Personally, I’d love to attend next year’s show in Tampa, Florida – but only if it is not once again held on the same week as DAC.
DAC Report – Latency; Platform as a Service; 262626; and ARM-12
Notes from my Tuesday DAC visits with CAST IP, Mentor Graphics, Dassault Systemes, Chipestimate.com, and Globalfoundries-ARM.
Here are but a few of the companies, hallway discussions, and presentations that I enjoyed during Tuesday at DAC:
1. Performance is a function of latency and power – as Gary Smith noted in his pre-DAC EDA and IP trends presentation. One example of the need to balance latency and power is in the application of real-time video streaming (e.g., H.264 video encoders). Latency is the delay that occurs between the processing and transmission of live video. A simple way to initially gauge latency is by waving your hand quickly in front of the camera and watching for blurring of the image on the display. I saw none during my demo.
Other news from CAST highlighted a joint announcement with IP company Beyond Semiconductor concerning an ultra-low-power, 32-bit BA21 embedded processor.
2. Hallway chat with Mentor’s M&A expert, Serge Leef:
Software as a Service (SaaS) for EDA cloud-based applications seems passé. Platform as a Service (PaaS) is the new “black.” The key driver in this change seems to be the push by next-generation chip designers for a more robust user experience (UE; see “Experience Required”). Serge sees the trend to user-experience designs as essential to the evolution of EDA tools. He even believes them to be a source of revenue in terms of a micro-business model.
3. Dassault Systemes offered several interesting technology demos. While their Netvibes product provides for intelligent dashboarding, Tuscany’s PinPoint enables tracking progress from synthesis to GDSII. In related news:
– IP protection and management includes synchronization of databases and documentation. In this way, a close partnership with Magillem is proving very useful. (More about this in the near future.)
– Simulation Lifecycle Management (SLM) for semiconductor verification and validation (V&V) flows may evolve quickly into a framework. The effort in the automotive industry via ISO262626 may establish a working model for the EDA industry.
4. Globalfoundries presentation at Chipestimate.com “IP Talks.” Subi Kerngeri, VP of the Advanced Technology Division, talked briefly about many things, mostly centering on the need to offer a combination of device technology design and SoC manufacturing expertise. But this need is fraught with challenges. (Reference: “Modular FinFET Increases Planar-to-Non-Planar IP Reuse)
He noted that Globalfoundries was the first fab to optimize for the newly announced ARM Cortex-A12 CPU – POP IP combined with Globalfoundries’ 28-SLP process. Also, Kerngeri emphasized the success of Fully Depleted SOI technology at 28 nm, saying that it was pretty much like bulk CMOS for designers. STMicro is their partner in FD-SOI. This technology has enabled 0.63 v at 1-GHz performance in a dual A-9 implementation.
Designer Experience Enhanced at Major IP Portal
Latest update enhances major chip design and verification IP access – evaluation site at Chipestimate.com.
Anything that improves access to and evaluation of critical intellectual-property (IP) blocks is welcome news to the system-on-a-chip (SoC) design community. Why? The main reason is that the reuse of verifiable design IP still provides the greatest cost savings for SoC designers. And cost remains a major constraint in the SoC process, as Gary Smith noted (again) in last night’s pre-DAC 2013 industry address.
One way to improve IP access is by going global. Over the last few years, the Chipestimate.com portal has done that by – in part – extending access to growing markets in Japan and China. Each of these portals provides native language access to IP from within local markets and beyond, to worldwide design centers.
Another way to improve IP access is through the expansion of content and resources. Today, Chipestimate.com announces a significant update to its main US website. Access to additional, key IP information is complemented by a new interface, which greatly enhances the SoC designer’s experience. In addition to improved search capabilities for IP queries, the update expands content by bringing together hundreds of ChipEstimate.TV videos, blog posts, technical articles, whitepapers, and more.
Check it out for yourself at www.ChipEstimate.com
IDF Beijing Highlights Intelligence and Networking
This year’s Intel Developer Forum (IDF) in Beijing, China emphasized a push toward intelligent embedded systems and communication-networking technologies.
Recently, Intel hosted another successful developer forum in Beijing, China. That event showcased the company’s business momentum and strategic views in intelligent embedded systems and communication-networking technology.
After the keynotes, a reporter from China’s CCIDnet interviewed Ton Steenman (Tang Diman), VP of Intel’s Architecture Group and GM of the Intelligent Systems Group. In this conversation, they explored the company’s business momentum in and strategic views toward intelligent embedded systems. Steenman noted that Intel does not intend to establish a standard or monopoly in the intelligent-systems industry. Instead, the company will work with industry partners to improve the security, connectivity, and manageability of embedded devices.
Still, it was apparent that the company will play a key role in the development of intelligent interconnections, including hardware, software, and cooperation with ecosystem hardware and software partners.
Intel’s Wei Chen and Ton Steenman (left to right) discuss trends in intelligent embedded systems. (Courtesy of CCIDNET.com)
Other interviews were conducted with Steve Price, Director of Marketing for the Communications Infrastructure Division, and Rajesh Gadiyar, Director of Embedded Architecture. Both speakers focused on the company’s technology advantages in the communications market. After the roundtables, attendant media were invited to visit the intelligence systems booths provided by Huawei and ZTE. (Related article: “Internet Minute Drives Packet Acceleration.”)
Huawei showcases it high-end, four-to-eight rack-mount server, which runs on Intel’s Xeon processors with up to 80 cores. (Courtesy of CCIDNET.com)
In terms of the networking-communication platform, Intel discussed the ease with which OEMs can integrate three traffic loads, including applications, control, and data-packet processing. The company claims that this integration will enhance product performance, lower costs, and accelerate time to market. In this way, Intel hopes to accelerate the transformation of the network system via virtualization, power management, and security.
Radios Reap Benefits of Ultra-Low Power and Digitalization
Wireless intellectual property from Imec, Renesas, and Silicon Labs is making headlines for advances in ultra-low-power and fully digitized radios.
Recently, Renesas joined Imec’s ultra-low-power (ULP) wireless-systems “Green Radio” program to enhance its short-range communication devices. This collaboration will develop multi-standard radio solutions for small battery-operated or harvested wireless-handheld devices. Aimed at the automotive and industrial markets, this technology combines clever architectures with low-power-design intellectual property (IP) to reduce power consumption by a factor of 3 to 10 compared to today’s radios. Imec’s ULP high-performance radios are compliant with wireless standards like Bluetooth Low Energy and ZigBee (both residing in the 2.4-GHz band). The market for ultra-low-power wireless communications is expected to grow with the rise of sensor networks in today’s prolific connection of embedded smart devices.
In related news, development of the elusive fully digital radio continues on many fronts. Recently, Silicon Labs laid claim to the industry’s first monolithic “digital radio on a chip,” providing a single-die antenna-input-to-audio-output digital-radio-receiver solution. Based upon existing software-defined-radio (SDR) technology, the monolithic receiver IC brings FM, HD radio, and DAB/DAB+ broadcast capabilities to a variety of audio applications.
Digital-radio technology enhances traditional AM/FM radio with data, such as program information, weather forecasts, news headlines, music artist and track names, and traffic information. To compete with traditional radio, however, the fully digital version must provide higher-performance audio sound with power-efficient RF technology. The former is achieved with improved intermediate-frequency (IF) downconverter-receiver IP architectures.
At the recent Globalpress Electronic Summit, Silicon Lab’s VP and GM, James Stansberry, explained the noise challenges in translating the receiver signal down to the baseband range. Readers may recall that IF downconversion issues have long plagued the modern wireless designer (see “RFICs Find Applications Everywhere“).
Others, most noticeably Intel, have recently claimed credit for the first fully operational wireless (Wi-Fi) digital radio.
The demand for continually lower-power and higher-performance RF chips will grow stronger in the coming world of wirelessly connected, embedded smart devices. IP that provides these two competing qualities will be in short supply.
Semiconductor Design Vs. the End-User Experience
Is it possible for semiconductor engineers to design directly for the end-user experience? Your comments are needed.
At a recent conference, Cadence’s Frank Schirrmeister noted that EDA companies have had to expand their coverage into the larger system market, thanks to changes in the semiconductor supply chain. Will this expansion ever reach end-product design (i.e., directly to the end user)?
Here’s another way of asking the same question: Will models/simulations/prototypes used by EDA-IP hardware and software engineers ever converge with similar models used by high-level product-development teams and end users?
Companies like Intel, Dassault, Cadence, Synopsys, Mentor, and others have tried to answer this question. Today, hardware customization – including SoCs and FPGAs – is done via software. (Stacked dies may still be the exception.) But something more is needed. How do we, as engineers, participate in designing the end-user experience?
I’d really like to hear your thoughts – especially by the end of this week. Please leave a comment here or send it to me: blyler@chipestimate.com. Thanks – John
How can left-brained (engineer) and right-brained (consumer) people come together to design useful electronic semiconductor products?
Reversing Moore’s Law; Interface IP; GPUs; Wafers Down
This “week in review” covers Moore’s Law in reverse, Cadence’s interest in interface IP, a game GPU video, wafers’ decline, and the dangers of armchair publishing.
I have several varied bits of news that might enrich your view of our semiconductor world:
* Moore’s Law Predicts Life Originated Billions of Years before Earth – Check out this way-cool thought experiment in which Moore’s Law is projected backwards to predict the theoretic chronological origins of life on Earth. For completeness, perhaps the projection should have been down with Wright’s Law (“Wright’s Law Edges Out Moore’s Law in Predicting Technology Development”).
* Cadence Challenges Synopsys on Interface IP – I’m sure you’ve read this announcement. Cadence is pushing into the interface IP market, offering a direct challenge to the dominant player – Synopsys. I won’t dwell on the business implications of this push, but rather note that it gives further weight to the growing importance of subsystem IP.
* Sean O’kane and I enjoyed a quick video chat with David Harold from Imagination Technologies at the Game Developers’ Conference. Among other things, Harold demonstrated his company’s GPU, which brings PC-quality gaming graphics to a tablet.
John and Sean interview David Harold from Imagination Technologies at the Game Developers’ Conference.
* DAC Commercial 2013 - DAC is just around the corner and at a new location – beautiful Austin, TX.
* Slight Decrease in 1Q2013 Silicon Wafer Shipments – The worldwide silicon wafer area shipments decreased during first quarter 2013 when compared to fourth quarter 2012 area shipments, according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry. The report notes that the first quarter is typically weak and that volumes are up relative to the same quarter last year. For the remainder of the year, it is hoped that the silicon industry will follow the projected modest growth in the semiconductor industry.
* Armchair Editors – At first, I was saddened by this article. It seems that everyone is becoming a publisher, further benefiting from the content generated by fewer and fewer real editors. Unfortunately, the original content source is not always cited and no compensation is paid to the original content creators (i.e., the Internet model). Apparently, Flipboard has just launched a new curation resource. Professional curators (another name for editors and writers) might be worried, as this resource encourages armchair publishers to further saturate the market. The end result is that established publishers will have less revenue to pay for original content. However, taken another way, it may mean that “professional curators” (like editors and writers) may further their own brand by using these same armchair-publishing resources.
* Are you looking for a good way to invest 5 minutes of your life? If you are an RF or analog/mixed-signal designer, I humbly suggest that you take a survey on RF chip technology.
CMMI Past Awakens Semiconductor Reboot
A visit near DoD Mitre territory reinforces the need for hardware and software capability assessment in the semiconductor market.
It was one of those moments when one catches a nearby dinner conversation and immediately has a flashback. For me, that flashback was to the windy desert that surrounds a DOE superfund cleanup site in Hanford, WA. It was the beginning of the new millennium. I had just helped to develop and implement one of the first Capability Maturity Model – Integration (CMMI) projects.
Let’s return to the present. Last night, I overheard several gentlemen at dinner talking about a CMMI assessment that they were conducting. Considering my location – just outside of Boston and deep in Mitre territory (think big DoD projects) – such conversations must be commonplace.
But CMMI discussions are seldom heard in the west – especially in Silicon Valley. That will change as the semiconductor world becomes more involved with software development (see “Google’s Software Process Challenges Semiconductor IP“).
I recently found another perspective that supports my push for CMMI-type assessments in the semiconductor space. Not surprisingly, this perspective comes from the automotive electronics market (“CMMI in Semiconductor Development”). As the amount of semiconductor-based hardware and software increases in automobile electronics, so will the need for new development and assessment processes.
Combined hardware and software assessments are coming to the semiconductor industry. It’s only a matter of time.
Long Standards, Twinkie IP, Macro Trends, and Patent Trolls
In Part II, IP Extreme’s Savage reveals why IP standards take so long while discussing brand values, macro trends, and changes wrought by patent trolls.
Blyler: Last time we talked, we covered the ongoing development of a soft IP standard. Should we expect an update in the near future?
Savage: The standard is in draft form and being reviewed among the technical contributors at Accellera. It’s just a matter of getting consensus within the EDA community and with the equipment manufacturers, who will need a mechanism to read the soft IP. What helps a lot is that this standard is based on the existing one for hard IP tagging. There are just a few extra things that needed to be added (to the soft IP standard).
Blyler: Please tell us more about those “extra things.”
Savage: One of the extra things proposed in the soft IP standard is the inclusion of export control information in the tag. That’s important in IP. For example, if the semiconductor IP has an Export Control Classification Number (ECCN), that information could be placed in the tag. It could then be discovered later on an actual device – perhaps in a (geographic) location where it shouldn’t be.
Blyler: Some have complained that the soft IP standard is taking too long to ratify. Any comments?
Savage: Things just move slowly in the semiconductor IP world – especially when you have interoperability with the EDA community. The challenge is that you need a handshake between the IP developers, the EDA companies who create the tools (that will need to make the [soft IP] machine-readable), and finally the semiconductor companies (who will actually be using the tools). You have to get all of those constituencies lined up. Like any standard, it takes a number of years before everyone agrees on the details and then gets the standard into widespread industry use.
Blyler: Has that process been made easier with all of the consolidations taking place in the EDA community? Do things move faster now because there are fewer players?
Savage: Surprisingly, the consolidation probably works against that. The problem is assessing a dollar value gain (to the soft IP). How much more can I charge if I support this standard? If you can’t answer that question, there is not a lot of motivation for EDA companies to invest in these things – especially in comparison to developing features for which people will pay extra money.
Blyler: Any other trends that you see?
Savage: We work with many companies to help create external channels for their internal IP. Lots of semiconductor companies talk with us about how to efficiently manage both their internal and external IP.
There is a nice video that Kevin Kline from Freescale did for us at our recent user event. One of his key points was that the value of the internal IP is worth more than the market cap of the company itself. It is analogous to Hostess Twinkies in that the value of the brand is worth way more than the Hostess factories. It’s similar with IP at large semiconductor companies.
I’ve had analysts call me to ask about the value of a specific company IP portfolio in relation to the competition. It seems that an increasing number of semiconductor companies are taking a more strategic view of their IP – beyond just the raw material and resources point of view. Within the next five years, I think that companies will think completely differently about their IP. This is a big macro trend – a new way of looking at IP.
Blyler: How do companies determine the real marketplace value of their IP? Is there an accepted benchmark or other means of open comparison?
Savage: The situation is very fluid. Look at the activities of Google and Motorola, where companies were being bought just for their IP. But their IP became a lot more valuable once Apple and Google started fighting it out in the marketplace (i.e., iOS vs. Android). A company’s IP may not have much value until something happens in the market. Then it becomes extraordinarily valuable. The big problem facing most companies is that they don’t know what IP they have. They might have this big opportunity because the market shifts and they are suddenly sitting on a treasure trove that they didn’t know they had.
Blyler: What about patent and IP trolls? I’ve seen companies that announced partnerships with certain patent houses and then, a month later, sued a competitor for patent infringement. I’m wondering what effect that has on innovation. Do you think patent trolls slow down innovation in favor of quick financial returns?
Savage: Most people have a pretty negative view of patent trolls – like the modern version of the highwayman. The troll analogy is quite good, as they seem to wait for someone interesting to appear. Then they pop out and ask for “your money or your life.” Inevitably, the industry will be heading for some kind of legislation to put some brakes on that activity – especially since there are a lot of people trying to get rich quick by specifically setting up practices to do patent trolling. It’s an extremely negative thing. But that is another reason why companies need to be on top of what IP they have. In these situations, you might have cross-licensing and such.
Blyler: Thank you.
Are Designers Really Affected by the Semi Supply Chain?
Do chip designers really need to worry about these external influences? Serus, Dassault Systemes, Mentor Graphics-Valor, and Open Silicon share their insights.
We live in a tumultuous world in terms of disruptive technologies, natural disasters, and global politics. Do chip designers need to worry about such seemingly external influences, as manifested by the global semiconductor manufacturing and supply chain? I asked this question of professionals in the manufacturing-supply-chain, product-lifecycle-management (PLM), board-level-design, and chip-design-services industries, respectively: Geoff Annesley, CTO at Serus; Brian Haacke, High Tech Industry Sales Director, Dassault Systemes; Michael Ford, Marketing Development Manager, Mentor Graphics–Valor; and Naveed Sherwani, President and CEO of Open Silicon. What follows is a portion of their observations. — JB
Blyler: Do chip designers really need to worry about the seemingly external influences of the global semiconductor manufacturing and supply chains?
Haacke: Designers do care about manufacturing with a primary focus on the impact of design rules provided by the foundries. The more design rules for which they are compliant, the more flexible they can be when choosing a foundry and mitigating risks if some natural disaster impacts one foundry over another. Regarding supply-chain influence, there are many aspects to consider. Designers would not be impacted by material supply disruptions because they typically do not ‘design in’ any of the materials used in manufacturing. However, a closed-loop feedback to designers on manufacturing test results – tied to requirements and design intelligence – can improve responsiveness to design-related issues impacting yield ramp-up.
Sherwani: It doesn’t require an earthquake or other natural disaster. In the coming move from traditional single-die chips to the era of 2.5-dimensional (2.5D) stacked dies, everything changes. With 2.5D, naked dies have to be tested and then placed on interposers and positioned into a single package. The industry has never tested or sold anything like this before. I think it will disrupt the normal supply chain and its well-understood chain of command.
Annesley: Design needs to be linked to execution in the global market. You need a feedback mechanism for companies to decide the best price and combination of packaging and manufacturing processes that result in the lowest-cost chip. That is a good example of tying back execution data to the design process and vice versa. For example, you have the material information for your design – be it chip or board. You may have alternates that you need to use (e.g., due to natural disasters). It is important for companies to track what actual alternates were picked for every component build. They will then have traceability and accountability with respect to the specifications.
Ford: Designers are motivated to create a product that meets the criteria set in terms of technologies, materials, costs, quality, life expectancy, etc. There is a significant influence on this from the manufacturing-production side, which - if not known by the designer – can result in variations in the product and the product not living up to expectations. Designing a product with some knowledge of the materials to be used and the actual production environment would give the designer the opportunity to design-in features that promoted better production quality, lower manufacturing cost, or reduced variation. Typically, though, the technologies of material choice and manufacturing capability are not visible in a way that designers can understand. So this does not happen except in rare cases. This is a clear opportunity for improvement.
About the Author
John Blyler writes the “IP Insider” blog at Chipestimate.com. He covers today’s latest high-tech, R&D and even science fiction in blogs, magazine articles, books and videos. He is an experienced physicist, engineer, journalist, author and professor who continues to speak at major conferences and before the camera on . John is the Vice President, Chief Content Office for Extensionmedia, which includes the brands Chip Design, Solid State Technology, Embedded Intel and others. He holds a BS in Engineering Physics and a MSEE. John plays the piano and holds a black belt in TKD.
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