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Hardware-Software Tops Priority List For ASIC Prototypers

Exclusive Research: Several surprises emerged from this year’s ASIC/ASSP FPGA-based prototyping survey. Most of them centered around both hardware and software issues.

The most important decision facing chip-prototyping designers this year (2012) concerned the completeness of the combined hardware and software platform (see Figure 1). Cost and boot time followed as the next most important issues. Close to 200 qualified respondents participated in the annual Chip Design Trends (CDT) “ASIC/ASSP Prototyping with FPGAs” survey.


Figure 1: Prototyping priorities are shown as listed in the 2012 CDT survey.

The concern over a complete hardware-software prototyping solution was in stark contrast to results from previous years. Then, key concerns revolved around the flexibility and expandability of the system as well as cost, performance, and ease-of-use factors (see chart below).

Another surprising finding in this year’s survey is the importance of system “bring-up time,” which ranked in the top three concerns for software-development-based prototyping systems. The importance of software-related issues was further verified by another survey question, which found that an overwhelming 65.5% of respondents used a combination of software and hardware execution (i.e., simulation plus FPGA prototyping).

What was the language of choice for these hardware-software co-designers? C/C++ beat out Verilog, VHDL, and their derivatives (see Figure 2).


Figure 2: These software languages are used in software simulation and hardware (FPGA) -based prototyping systems. (Source: 2012 CDT Survey)

Most designers who used a combination of software simulation and hardware FPGA-based prototyping did so to achieve early verification results (42.7%). Designers also were looking to accelerate the (simulation) speed with software processor models (35.4%).

The most common hardware configuration on the FPGA prototyping board consisted of between four and nine clocks (with the fastest clock running 50 to 125 MHz).

What interfaces were used to connect the software simulation and FPGA-based prototyping/emulation/acceleration platforms? Not surprisingly, ARM-based interfaces were the most popular (56.4%) including ACE, AMBA, AXI, AHB, or APB variations (see Figure 3). OCP was the choice interface for 17.3% of designers. Many software developers just didn’t know what interface was used (36.4%).

 

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John Blyler

John Blyler writes the “IP Insider” blog at Chipestimate.com. He covers today’s latest high-tech, R&D and even science fiction in blogs, magazine articles, books and videos. He is an experienced physicist, engineer, journalist, author and professor who continues to speak at major conferences and before the camera on . John is the Vice President, Chief Content Office for Extensionmedia, which includes the brands Chip Design, Solid State Technology, Embedded Intel and others. He holds a BS in Engineering Physics and a MSEE. John plays the piano and holds a black belt in TKD.