What do these tongue-twisting technical phrases have in common? They were all part of the morning session on the last day of the Hot Chips forum.
The catch-all title of “Technology and Scalability” was appropriate for the morning session of the last day at the Hot Chips forum. Michael Parker from Altera began the session by highlighting advances in the floating-point accuracy of floating-point-gate-array (FPGA) devices. FPGAs are inherently better at fixed-point calculations, in part due to their routing architecture. Conversely, accurate floating-point calculations are dependent upon multiplier density for the extensive use of adders, multipliers, and other trigonometric functions. Often, these functions are pulled from libraries to form an inefficient multiplier implementation.
According to Parker, Altera took a different approach by using a new floating-point fused datapath implementation instead of the existing IEEE-based method. The datapath approach removes the typical normalization and de-normalization steps required in the multiplier-based IEEE representation.
However, the datapath approach only achieves this high floating-point accuracy on smaller matrix functions (like FFTs), where low-power GFlops-per-Watt performance and low latency – thanks to enough on-chip memory – are the primary requirements.
Next up was Gregory Ruhl, who shared Intel Lab’s efforts to develop a Claremont-based processor prototype. He talked about the energy benefits of Near Threshold Voltage (NTV) computing using Intel’s IA-32, 32-nm CMOS processor technology.
Readers may remember the NTV processor (code-named “Claremont”) from last year’s Intel Developer Forum. My tweet from that show referenced a solar-powered Claremont demonstration in which the Claremont powered a short video clip of a playful kitten:
The Claremont relies on an ultra-low-voltage circuit to greatly reduce energy consumption. This class of processor operates close to the transistor’s turn-on or threshold voltage – hence the NTV name. Threshold voltages vary with transistor type. Typically, though, they are low enough to be powered by a postage-stamp-sized solar cell.
The other goal for the Claremont prototype was to extend the processor’s dynamic performance – from NTV to higher, more common computing voltages – while maintaining energy efficiency.
Ruhl’s results showed that the technology works for ultra-low-power applications that require only modest performance – from SoCs and graphics to sensor hubs and many-core CPUs. Reliable NTV operation was achieved using unique, IA-based circuit-design techniques for logic and memories.
Further developments are needed to create standard NTV circuit libraries for common, low-voltage CAD methodologies. Apparently, such NTV designs require a re-characterized, constrained standard-cell library to achieve such low corner voltages.
Finishing the session on “Technology and Scalability” was a presentation by Robert Rogenmoser from SuVolta, a semiconductor company focused on reducing CMOS power consumption. Rogenmoser talked about ways to reduce transistor variability for low-power, high-performance chips.
Transistor variability at today’s lower process geometries comes from the typical sources of wafer yield variations and local transistor-to-transistor differences. Such variability has forced the semiconductor industry to look at new transistor technologies, especially for lower-power chips.
What is the solution? Rogenmoser discussed the pros and cons of three transistor alternatives: FinFET or TriGate; fully depleted (FD) silicon-on-insulator (SoI); and deeply depleted channel (DDC) transistors (see Figure 3). FinFET or TriGate promise high drive current, but face manufacturing, cost, and intellectual-property (IP) challenges. The latter point refers to IP changes required to support the new 3D-transistor-gate structures.
According to Rogenmoser, FD-SoI transistor technology enjoys the benefits of undoped channels. But it lacks the capability of multi-voltages and a limited supply chain. According to him, DDC transistors were the best solution. This process offered straightforward insertions into bulk planar CMOS – especially from 90 nm to 20 nm and below. In terms of performance, DDC transistors are less variable with tighter corners. They also require simpler manufacturing steps. Equally important was the ease of migration of existing IP to the DDC process, he explained.
Rogenmoser concluded by explaining how DDC technology can bring back common low- power tools to lower nodes (e.g., dynamic voltage and frequency scaling, body biasing, and low-voltage operation).
Next week: The Rest of the Story