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Trends in Subsystem Semiconductor IP

As IP leads semiconductor growth, subsystem blocks cause node-based cost challenges, verification issues, hidden embedded cores, interface preferences, and more.

What’s new in the world of subsystem intellectual property (IP)? To find out, System-Level Design sat down with Richard Wawrzyniak, Senior Market Analyst for ASICs and SoCs at Semico Research Corp. What follow are excerpts of that conversation:

SLD: You mentioned that the cost of semiconductor IP at 20 nm and below is increasing. Why is that?
Wawrzyniak: The reason is complicated. For sure, the cost of hard IP (offered in a GDSII format and optimized for a specific foundry process) at lower nodes will increase due to changes in the actual transistor device—among other things. However, the cost of soft IP wouldn’t necessarily go up because it’s synthesizable (in a high-level language like RTL, C++, Verilog, or VHDL). Thus, the cost of soft IP is not really tied to the process node. Still, if an IP vendor needs to devote more effort to developing IP for a non-regular CMOS process, such as a FinFet device, the cost of even the soft IP might increase.

SLD: Wouldn’t significant changes in the device parameters of the SPICE model cause an increase in the cost of IP?
Wawrzyniak: There are two cost elements people often confuse when talking about IP. One is the license cost of the IP. The other is the cost to integrate that IP into the device - into silicon. What we are talking about is the licensing cost of the IP, not the integration cost. I would suspect integration costs will continue to rise. The only thing that might stabilize or even decrease the integration costs would be moving toward IP subsystems. The designer will then be using larger pieces of IP as opposed to lots of small discrete blocks.

SLD: You’re the expert on IP subsystems. Is it a growing market? What are the latest trends?
Wawrzyniak: More people are using subsystem IP, whether they have created it internally or licensed it from an IP provider like Cadence, Synopsys, or others. Overall, I see a rise in that activity.

SLD: Are verification hooks bundled into the subsystem IP?
Wawrzyniak: That’s where it gets a little hazy. With subsystem IP, designers license a system-level function, such as a communication subsystem. For example, an SoC designer might need several different types of communication protocols - including HDMI, MIPI, etc. - for a consumer device. The designer could get all of the functions as discrete blocks and throw them together, or he/she could license a complete communication IP subsystem from a vendor as one contiguous block. This subsystem IP block could then be tested in parallel with IP that the designers must create in-house. The verification suites also could be run in parallel on all discrete and system IP blocks. Theoretically, the designer could cut down on his/her total verification effort. If you reduce this effort, then theoretically, you reduce the total cost of integration.

Unfortunately, if you give designers more headroom, they often use it all up – plus a little extra. So theoretically, you may not reduce the cost of the effort at all. Instead, it might end up being more expensive. But in exchange for that incremental increase in cost of integration, you end up with a device that has much more functionality. That is a main driver behind the subsystem concept.

SLD: The growth of IP continues to outpace the overall semiconductor-market growth rate. This refers to blocks of discrete IP. If designers are increasing their use of subsystem IP, would you expect the resulting bundling of IP to cause a decrease in the IP growth rate?
Wawrzyniak: That might happen, but farther down the road. We are just beginning to see actual commercial subsystem products and licenses. So that effect, if it happens at all, will not happen for quite some time.

SLD: Sensors are being incorporated into every imaginable device. Are you seeing any growth in the sensor IP market?
Wawrzyniak: The problem is that most sensors are based on a microelectromechanical-systems (MEMS) process. For sensors to be a viable market, where you can license the function, you have to have access to a MEMS process technology. That part of it hasn’t evolved yet. Instead, most designers that use sensors in cell phones and the like buy a MEMS chip that contains all of the sensors. These companies buy the chip from a vendor that has access to the MEMS process and puts all of the sensors into silicon. That’s not the same thing as today’s traditional IP market. I don’t think we are quite at the point where you can actually go out and license sensor IP as IP that can be included in an SoC design—but the time is coming.

SLD: From your research, what are the major IP growth categories?
Wawrzyniak: I break the IP market into 10 buckets or categories: memory, CPU, DSP, graphics, analog, interface, logic, chip enhancement, interconnect, and security. Each of these IP categories is further broken into licensing, royalty, and service revenues. Since people haven’t yet reported for Q4 2012, these numbers are just a forecast for on-chip IP revenues:

> CPU: $1B
> Interface: $600M
> Memory: $400M
> Other: $1.4B
> Total IP market = $3.4B in 2012

An interesting footnote concerning on-chip interface IP is the ongoing and increasing importance of Serializer/Deserializer (SerDes) communication channels. Designers are moving away from parallel connectivity and toward the higher performance of SerDes channels. Most people think of SerDes as a real heavy-lifting analog mixed-signal (AMS) technology, which it is. But SerDes also has a digital side, which has a MAC and a PHY. Most designers would not contemplate licensing the SerDes PHY from one vendor and the MAC from another. They are optimized to work together. That’s why I include SerDes in the interface and not the analog category.

SLD: Are the number of cores continuing to increase in mobile devices?
Wawrzyniak: There is a growing dichotomy between cores that are embedded in devices and cores that are programmable by the user. For example, a smartphone might have a number of well-known cores from ARM, Qualcomm, etc. But behind those publicly stated cores are many other embedded cores. The user is unaware of them because they cannot get to them—cores from Tensilica, CEVA, Imagination Technologies, and so forth. That trend is only going to increase.

SLD: Are the major core providers using these embedded cores as part of their subsystem IP?
Wawrzyniak: That could be. My point is that there is more activity than just the major IP providers. They are the largest players and thus the most well known, the most visible. That’s great. But they are never alone in a device. There are always other embedded cores in the same device doing different functions. That trend will increase.

In the long term, this means that the number of IP cores being used in devices will go way up. It is already going up. But it will go even farther, which again makes the argument for subsystem IP. Why deal with 200 separate IP blocks spread around the device instead of dealing with 10 equivalent subsystem blocks? In terms of functionality, there would be no difference. But from an expenditure of effort, there is a world of difference.

Originally posted on the System-Level Design portal.

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John Blyler

John Blyler writes the “IP Insider” blog at Chipestimate.com. He covers today’s latest high-tech, R&D and even science fiction in blogs, magazine articles, books and videos. He is an experienced physicist, engineer, journalist, author and professor who continues to speak at major conferences and before the camera on . John is the Vice President, Chief Content Office for Extensionmedia, which includes the brands Chip Design, Solid State Technology, Embedded Intel and others. He holds a BS in Engineering Physics and a MSEE. John plays the piano and holds a black belt in TKD.