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Shadow Supply Chain Demands System-Level Verification

Counterfeit memory chips may be the cause of Russia’s Phobos-Grunt space mission failure. Perhaps a truly system-level verification approach would help.

Watch out for more failed spacecraft debris falling back to Earth, courtesy of the shadow supply chain!

A recent IEEE Spectrum article highlights the danger of substandard parts in mission critical applications like spacecraft. Many feel that engineers are to blame for the failed Russian space mission by specifying inappropriate, low grade parts. But others point out that counterfeit memory chips were intentionally misrepresented as being of higher performance grade than advertized.

Russia’s first attempt to reach Mars – the Phobos-Grunt spacecraft.

Counterfeit chips seem to be a growing problem in the electronic design for all markets. Such counterfeits are part of the shadow supply chain. One of the more recent cases involved $16M in counterfeit chips from China and Hong Kong that were sold under major brand names to almost all segments of the U.S. electronics industry – from mission critical military and medical systems to consumer goods.

Would a more robust, system-level verification approach have discovered the low grade memory chips on the Russian spacecraft? Probably not, since the official report suggests that the engineers specified military grade (non-radiation hardened) instead of space grade components. Still, it appears that even the specified military grade chips were of questionable quality – illegal substitutes from the global “shadow supply chain.”

No engineer worthy of their hard-earned title would knowingly use inferior parts in his/her designs. For example, semiconductor IP designers don’t include third-party IP that isn’t verifiable. Extending the idea of verification to include traceability, there is even a standardized tagging mechanism that defines the ownership and origin of IP. From the Accellera site: “This standard provides a way to track both hard IP and non-hardened or soft IP information throughout the design and development process.”

Verification of the integrity and quality of integrated circuits (ICs) is one thing. The safeguards used in the design process must be extended to the manufacturing side. Beyond that, the rest of the product creation chain must build upon the safeguards of the chip designers. Some of these safeguards already exist. For example, board-level development employs a number of tools to identify and verify the integrity and ownership of firmware and RTOS (see “Embedded Software Developers Need Their Space”).

But this is where things get dicey. Counterfeit parts look just like their original, legal brethren. It seems as if only two ways exist to ensure that designers are using original parts. First, just like FedEx or UPS packages, every part should have a unique identifying and traceable number. Second, IP tags should be accessible from every chip, perhaps via the testing pins on the chips.

Even such improvements would not be enough if emerging countries don’t enforce globally recognized copyright and patent laws. (see “”). In this way the semiconductor industry is wrestling with the same issues as the music, publishing and entertainment industries.

The semiconductor industry does a good job providing verifiable IP at the RTL and chip level. Those safeguards should be extended to the board- and final product-level development process, thus providing a true system-level verification approach. Unfortunately, getting approval for such an encompassing approach would mean crossing too many discipline and development domains to be practical. But incremental improvements should be attempted between the chip, board and product verification interfaces.

In the mean time, counterfeit components – thanks to the shadow supply chain – will keep us watching the skies for falling spacecraft debris.

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About the Author

John Blyler

John Blyler writes the “IP Insider” blog at Chipestimate.com. He covers today’s latest high-tech, R&D and even science fiction in blogs, magazine articles, books and videos. He is an experienced physicist, engineer, journalist, author and professor who continues to speak at major conferences and before the camera on . John is the Vice President, Chief Content Office for Extensionmedia, which includes the brands Chip Design, Solid State Technology, Embedded Intel and others. He holds a BS in Engineering Physics and a MSEE. John plays the piano and holds a black belt in TKD.