Data from Globalfoundries and an independent CDT survey confirm growth in RF silicon designs, III-IV challenges, and trends in power-amplifier techniques.
Earlier, I reported how RF devices benefit from overall low-power mobile trends and increased digitalization. Now, a recent paper and survey reveal which digital implementation processes are gaining popularity and which specific low-power amplification techniques are favored by semiconductor intellectual-property (IP) designers.
A few months back, Globalfoundries engineers Fayyaz Singaporewala and Peter A. Rabbeni provided a Chipestimate.com Techtalk presentation entitled, “Data at the Center of RF Foundry Growth.”
In their paper, the engineers discussed the flexibility of silicon-based RF chips: “Although the Johnson limit dictates the limitation of silicon in comparison to more traditional RF technologies like III-V’s, the ability to integrate RF with digital control provides designers the capability to innovate in ways never thought of and approach or even exceed the performance of these traditional technologies (see Figure 1).
The recently completed “Chip Design Trends” (CDT) RFIC survey confirms the popularity of the silicon implementation of RF devices (see Figure 2). For current designs, more respondents listed silicon (66%) followed in order by GaAs (32%), SiGe (27%), GaN (23%), and InP (10%). For future designs, more respondents listed silicon (66%) followed in order by SiGe (31%), GaN (28%), GaAs (16%), and InP (13%). [The “Chip Design Trends” 2013 RF-MW tools survey targeted developers of products in RF and analog/mixed-signal (AMS) ICs. A total of 129 qualified designers responded to this survey.]
From both the Globalfoundries data and CDT survey, it’s clear that silicon remains a popular implementation choice for RF and microwave IC designs. Also evident from the Globalfoundries data – although not queried in the CDT survey – is that many fabs and fabless companies are looking at alternative device implementations, such as silicon-on-insulator (SOI) for both analog RF and digital apps.
Predistortion trends offered another point of comparison between the Globalfoundries paper and the CDT survey. The engineers from the foundry noted that the application of DSP concepts to RF applications is not new, “but the advancements in digital processing have reached a point where the benefits of these concepts can be efficiently realized.” Some emerging examples of these concepts include envelope tracking, tuning, and predistortion. Again, these are not new concepts, but it is only now that silicon technologies have advanced to a point which makes the application of these concepts to RF possible.
The CDT survey asked the following question: “If a discrete power amplifier (PA) is part of the RF front-end subsystem, then please rank the techniques that you would use to improve the efficiency of the PA.” As the results show (see Figure 3), digital pre-distortion is still the preferred technique for improving PA efficiency. Even though envelope tracking has received a lot of attention in the media, it ranks low in terms of priorities for PA development.
Low-power trends in high-growth areas like the mobile consumer market are driving the popularity of specific RF implementation processes and power-amplification techniques. The explosion of analog-digital smart sensor (or sensor fusion) devices should also accelerate these trends.
In this monthly video with Sean, I highlight embedded processors and future wearable sensors on the raceway to CPU heatsinks, Microsoft depth sensor chips, and Google Glass technology.
Sean: I heard you were at the Sonoma Indy race over the weekend. Wasn’t there a pit accident that sent one of the crew members flying into the air?
John: I was in the press room when the pit accident occurred. You should have heard the uproar from the other editors – conjecturing on motivations and the ultimate effect of the incident. I wish we could generate some of this same excitement at our Design Automation Conference (DAC). Maybe at next year’s DAC 2014 we need some kind of racing event – sans the accident.
This incident probably cost Scott Dixon a victory. Instead, Will Power won the race. Members of Power’s pit crew were the ones affected by or causing the accident – depending upon your point of view.
Sean: I’m glad that no one was seriously injured. But what does Indy racing have to do with EDA and IP?
John: Today’s high-end cars contain over 60 embedded processors. The Indy cars – especially when fully instrumented – have many more sensors and data-acquisition/telemetry components. Integration of all the hardware and software needed to make commercial and Indy cars perform correctly is no small task. It takes a lot of simulation, modeling, verification, and IP. [Shameless plug: I’ve just finished a Progress-in-Technology (PT) series book for the Society of Automotive Engineers (SAE) that deals with many of those issues. It will be available in November 2013.]
Who knows, maybe the pit accident wouldn’t have happened if the crews wore proximity sensors in their clothing. Semiconductor giants like Apple, Google, Samsung, and others are making a big push for wearable wireless accessories.
On final comment: I want to thank Mouser Electronics for helping me obtain a press pass for the Indy Race and for sponsoring the Hot Chips conference. This support has afforded them a great way to gain the attention of the semiconductor industry.
Sean: Let’s move on to the Hot Chips conference, which returned this year to the Stanford campus. Hot Chips is a symposium on high-performance processors. Last year, you talked about transistor variability, FinFet structures, femto cells, the decline of silicon IPOs, Wright’s vs. Moore’s Law, and more. (Wright’s is a more expansive trend of technology evolution.) What was new this year?
John: As you noted, Hot Chips is really about processors – from graphic processing units (GPUs) and accelerators to multicores and traditional “big iron.” This year was no different, but there was an expansion to cover more consumer applications. Here are just a few highlights:
Microsoft Xbox One
Sean: Thanks again for your monthly update on what’s new in the world of semiconductors and IP.
John: My pleasure – thanks!
Cars, electronics, and the race make for a great day at the Sonoma Indy raceway.
It was an exciting race for the fans, but a challenging one for the drivers. And not without more than one incident: “Controversial penalty, pit-road accident costs Scott Dixon IndyCar win.”
Personally, I was cheering for Tony Kanann’s team (#11) – sponsored by Mouser Electronics, among others. I had met Kanann earlier at one of his Indy 500 victory celebrations shortly after this year’s DAC 2013.
Why am I covering the race? Did you know that one Indy car conservatively costs about $375,000 for a rolling car – to which is added over $100,000 worth of electronics (hardware, software, sensors, and the like)? All of these chips, boards, and networks use design and verification interface IP. Automotive electronics are where chip and embedded electronics meet the road! (Sorry for the lame pun, but I couldn’t resist.) I’ll post an interview with one of the engineers maintaining the car during my next blog.
Lessons learned in both global automotive-product and process-intellectual-property management and outsourcing ring true for the semiconductor world.
While perusing the Society of Automotive Engineers (SAE) International’s vast vault of peer-reviewed papers, I chanced upon one about intellectual property (IP) and outsourcing. This work uniquely focused upon broad issues in both product and process IP protection. Conversely, many of my automotive-related stories understandably concentrate on specific hardware-software issues (see “IP’s Silent Presence in Automotive Market”).
The system-level view of both product and process outsourcing yielded many heuristics that apply to both the automotive and semiconductor IP markets. I won’t reveal all that this paper had to offer, but just enough to highlight these key best practices.
This SAE article provided justification and a solution to reduce both product and process IP in a global design and manufacturing environment. You can read the entire paper by visiting: “PLM Promotes a Smart Outsourcing Model that Balances Cost with Intellectual Property Protection” by Bob Brincheck – Dassault Systèmes.
And yes, there is a fee for this paper that helps fund further work while reducing the risk of content theft. High-value intellectual property must be guarded in all of its various forms – from electronic design to useful articles about technology.
“Coincidences mean you’re on the right path.” – Simon Van Booy, Love Begins in Winter: Five Stories
I was looking for an example of a “pure software environment” when my Google search led me to the Pure “software” division of Imagination Technologies. As you know, IMG (London Stock Exchange symbol for the company) is well-known for its communication and graphic-processing-unit (GPU) intellectual properties (IPs) – plus the recent acquisition of MIPS.
Apparently, IMG’s Pure division creates actual consumer products, namely digital-audio-broadcasting (DAB) radios (i.e., Internet radio). These devices utilize many of the company’s IP cores. In addition to product revenue, these radios help to validate IMG’s Meta, Universal Communications Core, digital radio, and audio technologies. According to the website: “Pure is the world’s leading manufacturer of DAB digital radios and the number-one supplier of radios in the UK.”
It’s noteworthy when a semiconductor IP company can and does make actual products!
But why was I interested in pure software in the first place? It was in regards to a student’s observation about pure vs. embedded software during the verification phase of the hardware-software life cycle.
“Pure” is a term you seldom use in discussing almost any hardware-software system, in part due to software-hardware symbiosis. Pure software generally refers to software that is relatively removed from hardware concerns (e.g., at the application level). For example, in a purely software environment, a system could be simulated without the use of hardware-in-the-loop techniques – as in the verification and validation of automotive hardware and software electronics.
Conversely, in an embedded environment, a verification engineer must consider details of the hardware in the simulation to access discrete I/O signals and deal with the response latency from interrupt handlers. No such concerns are associated with pure software simulation, in which the hardware details are abstracted away (via a model) to enable focus on just the software issues. For these reasons and others, testing in a purely software environment is usually easier than a hardware-software one. After all, the physical constraints imposed by the hardware interface are not an issue (in pure software testing).
My quick Google research did yield the following reference example: “Automatic Generation of Hardware/Software Interfaces” by Myron King, Nirav Dave, Arvind, MIT.
“Modern mobile devices provide a large and increasing range of functionality, from high-resolution cameras, video and audio decoders, to wireless basebands that can work with a variety of protocols. For power and performance reasons, much of this functionality relies on specialized hardware. Often, designers start with a pure software (SW) implementation of an algorithm written in C (or Matlab) and identify computationally intensive parts, which need to be implemented in hardware in order to meet the design constraints. Hardware (HW) accelerators come in three different forms. Hardware can be synthesized as an ASIC for the application at hand….”
“To compare the performance of our language to more conventional methods of HW/SW codesign, we implemented the pure software partition (F) in SystemC and manually in C++. We chose SystemC to establish an upper bound since it is widely used in HW/SW codesign (though generally in the modeling of systems), and the performance is considered by some to be realistic enough to drive design decisions. We chose manual C++ as a lower bound, since this is how embedded devices are commonly written. The SystemC implementation is roughly 3x slower due to the required overhead of modeling all of the simulation events. The manual C++ version is slightly faster than the generated one, as it avoids all discarded work or need for shadow state.”
The relationship between my search for pure software examples and IMG’s consumer-product division was purely accidental (i.e., a coincidence). Still, there might be some clever marketing folks at IMG who disagree.
A recent Financial Times (FT) article doesn’t mince words in calling China’s “international theft of inventions part of a national business model.” According to the story, China is following an approach long sanctioned by many other Asian countries.
This article, penned by Mark Anderson, chief executive of Strategic News Service, begins with the recent identification by Mandiant – a cyber security specialist – of the theft of foreign intellectual property by a Chinese army unit. But the author notes that Japan in the 1970s was the first practitioner of this new “information mercantilism.” These activities led to the unwanted IP transfer of four US technologies: TV, DRAM, video recording, and steel production. Within a few years, these industries disappeared in the US. Since then, South Korea has adopted and refined this model, explains Anderson.
Everyone in the semiconductor industry knows the critical importance and financial value of IP. It is not hyperbole to write that IP theft is ruining countries and shifting both military power and economic wealth in ways that were previously unimaginable.
I encourage readers to contemplate the entire FT article and its growing list of comments. You may need to take a brief survey or even pay a very small fee to access the complete article. But it’s well worth the price. Besides, you don’t want to spread the Internet’s “content mercantilism” by stealing good stories without paying for their creation.
Major but lesser covered topics at Semicon West 2013 are the focus of this short video chat between Sean and John.
This video deals with a few of the less-covered, but still major topics at Semicon West:
› If innovation occurs at the boundary of disciplines, when is the best time to handle IP issues among the potential collaborators?
› Did you know that MEMS and microcontrollers are being fused together? Or that Google Glass incorporates five MEMS sensors? A contact lens version is also being researched.
› The “end of Moore’s Law” is a tired expression. Still, the cost efficiency of transistors is decreasing at the lowest nodes. TSMC is pulling back on estimates for FinFets. Many fabs and fabless companies are looking at alternative device implementations, such as silicon-on-insulator (SOI) for both analog RF and digital apps.