Here are a few quick bits from my experiences at the ARM Developer Summit (@ARMDevSummit), part of ARM TechCon. I will write about each in greater detail later on. – JB
Stacy Smith, Developer Education Tech Lead/Sr. Developer, spoke @ARMDevSummit: “Desktop #GPU is square, mobile GPU is triangular so power is compartmentalized.” Granted, she was providing a geometric analogy for conceptualized power demands. Still, it was a great visual (dare I say, “graphic”) aid in Stacy’s presentation.
Hauntheim demos feature many graphic features and clever use of buffers. And just in time for Halloween!
John Leroy, IP Attorney for Brooks-Kushman, talked about the challenges that open source presents to the semiconductor and hardware-software supply chain. The key takeaway was that open-source software is “free,” but with a few conditions that software developers really need to understand.
Sean O’Kane (from Chipestimate.TV) and I look over all of the cool Internet-of-Things (IoT) apps on the show floor, including ARM’s connected key. Watch for that video.
From Brian Fuller’s tweet: Caption: Beauty (ARM’s Tiffany Sparks) and the beasts. @ARMCommunity @chipestimate #armtechcon @JohnBlyler pic.twitter.com/h71vj9MmKi #semieda #semip
Two rumors about Qualcomm, Arteris, and DSP architectures lead to tantalizing speculation about a new type of DSP-based IP subsystem.
Rumors are tricky things – hard to prove but sometimes harder to disprove. Experience has taught me that the best way to judge technology-based rumors is by looking for convergence. Here’s a case in point: John Cooley at DeepChip has posted emails suggesting that Qualcomm may be engaged in an asset buy with network-on-a-chip (NoC) company Arteris.
This rumor must be weighed in the context of today’s semiconductor intellectual-property (IP) environment. It isn’t unusual for smaller companies to be acquired by larger ones –ostensibly for their IP. Conversely – or to encourage such an acquisition – smaller companies are licensing more and more of their in-house IP for external sales. Why? Kevin Kline from Freescale has noted that the value of the internal IP of a smaller company can be worth more than the market cap of the company itself.
But legal IP guru Jonathan Kaplan once told me that, in general, IP holdings are more valuable to smaller rather than very large companies. If that’s true, why would an IP giant like Qualcomm seek to acquire Arteris?
To answer that question, let’s consider another rumor that Qualcomm may license its digital-signal-processing (DSP) architecture. If this supposition proves accurate, the company will join a trend among other multicore-processor giants (e.g., IBM licensing Power CPU; nVidia licensing its GPUs; and Imaginations licensing MIPS).
Does Qualcomm’s rumored interest in Arteris – plus the rumor that Qualcomm may license its DSP architecture – provide evidence of a convergence? That is hard to tell, as we lack a legitimacy weighting for each rumor. Still, they do seem to point to a convergence. Acquiring Arteris’s chip-level interconnect IP might make it easier to integrate Qualcomm’s DSP IP with other non-company cores on a heterogeneous system-on-a-chip (SoC). This is only speculation, as Arteris’s competitors may disagree with the ease-of-integration assertion.
Still, if these two rumors are true (and that’s a big “if”), chip designers may see the emergence of a new DSP-based IP subsystem. Or so it’s rumored.
Do you remember developing on the 6502 processor? How about Acorn’s BBC Micro? Well, surely you’ve heard of ARM. If you answer “no” to any of the above and are interested in developing for the Internet-of-Things (IoT), this video will help.
Two distinct IP functional groups vie for strong growth in the future. Which one will win?
Here is the second part of my interview with Rich Wawrzyniak, Senior ASIC and SoC Market Analyst for Semico Research. Previously, I followed up on a Semico Research report predicting that the compound annual growth rate (CAGR) for the third-party semiconductor-intellectual-property (SIP) market would exceed 19% from 2013 to 2017.–JB
[Blyler] Where is the increase in third-party semiconductor SIP (i.e., analog, digital, interface, etc.)?
[Wawrzyniak] The increase in SIP revenues shown in this just-released Semico Research report on the SIP market is really not limited to any one area. There is strong growth in the following areas: CPU, memory, graphics, analog, interconnect, and security. There is good growth in interface, logic, DSP, chip enhancement, and audio. I make the distinction in the two groups because the first group is growing faster than the second group. This is due to the nature of the systems-on-a-chip (SoCs) being designed for today’s applications.
Mobile devices need connectivity, processing power, and good graphics. All of these factors are increasing in functionality. As the computational resources increase, so too must the resources that support the computational functions. Included in this trend are IP types like graphics, security, and interconnect. All of these types are necessary to support the feature sets and functionality required by device users.
Quarterly Growth Rates by IP Category
|13 / ’12|
|Total Percent Growth||6.2%||6.0%||5.2%||4.5%||21.1%|
*Forecast Source: Semico Research, 10/13
This table shows what the 2013 quarterly growth rates have been and are expected to be for the balance of the year. The 2013 yearly growth rate is given with a total SIP market growth rate for 2013.
As you can see, the third-party SIP market is doing very well. This trend is reinforced by the gate-complexity growth chart above. That increase in complexity is being facilitated by the use of more and more IP in each SoC silicon solution. Without the use of IP, it is doubtful that these levels of growth in device complexity could reach the levels they are at today or be sustained over the forecast.
Semico believes this trend will continue for the foreseeable future. IP-market growth rates will probably fluctuate somewhat from what is projected. But it is certain that the long-term trend is upward, as more designs use more IP over time.
Walter Knight’s latest romp includes cameos by Cadence, former CEO of Chipestimate.com Adam Traidman, and veteran writer Max Maxfield.
Who would have known? Two of our fellow engineering brethren now belong to the ages! They have transcended the everyday world of semiconductor affairs to become characters in Walter Knight’s latest book. Who is this author, you ask?
“Knight is a world-famous science-fiction writer,” proclaims Lieutenant ATM, a futuristic sentient being created with “the newest Cadence microchips.” ATM, the pseudonym for real-life entrepreneur Adam Traidman, is a time-traveling artificial human being in the author’s nineteenth installment of the hit online book series, “America’s Galactic Foreign Legion.”
Soon to be an MTV mini-series (Okay, I made that up), the other semiconductor star is bebop boolean author Max Maxfield, who assumes the role of Bank of America CEO. Here are a few memorable passages from the author’s latest (19th) work:
“My last name will be Traidman. Adam Traidman. It has a nice ring to it, don’t you think? I will move to Silicon Valley and become a computer and software engineer. I will invent and trade computer chips for money. Money is as good as cash. Help me get started and blend in, and we will be rich beyond your wildest dreams.” “Move to San Jose?” scoffed Tonelli. “I heard about that dump. It’s going to fall into the Ocean. No way, to Jose.” “Trust me,” insisted Atm. “Fate reaches out and extends its hand. In 1955, computers are the future. We’ll bulldoze the orchards and make Santa Clara County a silicone paradise. It’s only a matter of time.”
“Adam Traidman cleaned up well. He approached Max Maxfield, CEO of Bank of America, about financing proposals to develop and build a talking automatic teller machine. Traidman provided blueprint designs for revolutionary silicon-based micro-computer chips, a standardized computer operating system, cell phones and towers, satellite technology, fiber optic relays, Starbucks coffee, thirty-one new flavors of ice cream, and cable TV.”
Knight’s books are fast-paced, easy-to-read romps that weave contemporary themes and characters within futurist settings. Pick up a few online for your next business trip, weekend diversion, or book-and-booze club review.
Projected growth in the third-party semiconductor intellectual-property (IP) market through 2017 may affect the direction and evolution of subsystem designs.
Earlier this week, Semico Research issued a report predicting that the compound annual growth rate (CAGR) for the third-party semiconductor-IP (SIP) market would exceed 19% from 2013 to 2017. To understand more, I asked specific questions of Rich Wawrzyniak, Senior ASIC and SoC Market Analyst for Semico Research. What follows is his response.–JB
[Blyler] Does this increase in third-party SIP revenues help or hinder the development of IP-subsystem packages?
[Wawrzyniak] This is a very interesting question, and the answer can have far-reaching implications for many companies – both IP vendors and users. In Semico’s view, the growth in revenues for the discrete third-party SIP market is nothing new. It has been occurring for some time, driven by the rise in complexity in system-on-a-chip (SoC) silicon solutions. More designs are being done using the SoC design methodology. And in those designs, more IP is being used. This rise in device complexity accounts for the growth in the IP market.
The IP-subsystem market is just emerging – again, being driven by the rise in SoC complexity. SoC design costs for silicon and software are also rising. For the first time, in 2012, software design costs outstripped silicon design costs. SoC designers are looking for ways to reduce the level of effort and cost they need to expend in order to create these complex silicon solutions. At the same time, they want to increase functionality and performance. IP subsystems are the means to accomplish that task.
At the current time, I do not see anything on the SoC-design landscape horizon that will markedly reduce the level of effort that designers are expending – except the use of IP subsystems.
So will growth in the discrete-IP market hinder or delay growth in the IP-subsystem market? Semico does not believe so, as we are in the very early stages of IP-subsystem market development.
(Toward this question and others, Semico is hosting a conference on the IP ecosystem at the Double Tree Hotel in San Jose on November 6. We will be addressing this question and more – all related to the central issue of IP market direction and evolution. You can find more information about our conference here.)
One common thought circulating about the development of the IP-subsystem market is that its growth will cannibalize the revenues of the discrete-IP market. We at Semico do not believe this to be the case. The reason lies in why the IP-subsystem market is developing in the first place.
We need to remember that the larger semiconductor companies – say the top 15 to 20 – have been internally developing their own IP subsystems in the form of system-level functions for the last several years. Now, this concept has migrated over to the discrete-IP market, and we see several IP vendors developing and deploying their own products into the marketplace.
Why did designers at the top-tier semiconductor companies do this to begin with? As design complexity and costs increased, they sought ways to reduce the level of effort they were expending to create these system-level functions out of discrete IP blocks. They reasoned it was much better and more efficient to deal with the design efforts in larger pieces instead of trying to spend the same effort acquiring, managing, and integrating 200+ discrete IP blocks into their designs. Because the IP subsystem is one complete, contiguous system-level function in the form of one block, it can be reused much more easily than trying to disaggregate and then re-aggregate multiple IP blocks that make up that system-level function. The IP-subsystem concept was born.
The following chart makes it easy to see why this is happening. This chart was developed from other research Semico has conducted on the ASIC and SoC design-starts landscape. It looks at the average gate-complexity level by device type over the last 11 years with a 5-year forecast. This specific chart looks at the average gate count in three types of SoCs. It is driven by looking at the use of these SoCs in 70 end-market applications. So it is the number of designs for each product type – in all the applications we track – multiplied by the gate count in each part type, and then averaged across the total for each year.
The spike in the growth rate from 2002 to 2007 is caused by more designs switching over to the SoC design methodology. Because it is coming from a small base, the growth rate at the beginning is high. It declines around 2008 due to the impact of the “financial meltdown.” (Designs put on hold or cancelled outright equaled fewer designs being done in this timeframe.) Even with the reduction in the number of designs, the growth rate was still positive.
Then, starting in 2011 – after the markets stabilized and had started to recover – gate-complexity growth rates started to increase once more. The forecast years of 2013 to 2017 see a pickup in growth rates in response to increased transistor budgets, which were made possible through use of the newer process geometries and the continued need for more functionality. In this case, functionality drives complexity. This, in turn, drives the use of more IP and eventually, the evolution of the market to the use of IP subsystems.
As an aside to this chart, it’s important to note that from 2008 to 2010, many architectural refreshes (as embodied by first-time design efforts) were put on hold until the market showed signs of recovery. This was due to the fact that most companies will take the opportunity presented by a first-time design to invest the most time, effort, and money in developing the architecture they want to carry them for the next two to three years. The financial meltdown forced many companies to curtail these efforts and stretch these architectures further than they would have liked. Now that these efforts restarted toward the end of 2011 and into 2012 and 2013, there is a great deal of ‘catching up’ to do. That means the use of even more IP to provide the functionality needed in these new designs: again, another solid driver for the IP market.
Semico doesn’t see this trend ending anytime soon. Consumers of electronic devices – whether mobile or stationary – are asking for more connectivity and the feature sets to take advantage of that connectivity. This means more complexity in the solutions powering these devices. Given this trend, it is easy to see why IP market revenues are growing and – given the increase in design costs – why the IP-subsystem market will continue to gain importance over time.
[Blyler] Thank you.
Look for Part II of this story in my next blog.–JB
A few EDAC export-control experts save the EDA industry from potentially devastating technology, IP, and encryption regulations.
A few nights ago, I learned about a new breed of EDA industry heroes. They are not the brilliant mathematicians, physicists, or engineers who create elegant and highly efficient algorithms. Nor are they the system architects who integrate complex tool flows.
The heroes I mention are the professionals who have waded into the murky waters of government bureaucracy, legal processes, special-interest lobbyists, and politicians to keep EDA technology as free from red tape as possible. I refer to the few, the proud, the “export-control” specialists.
One such champion is Larry Disenhof, Cadence’s Group Director, Export Compliance and Government Relations and Chairman of the EDAC Export Committee. Last month, I interviewed Disenhof concerning the importance of export control. This interview was a prelude to a recent webinar in which Disenhof examined the current state of export regulations and their effect on the EDA community. What follows are just a few highlights from that tutorial:
Data from Globalfoundries and an independent CDT survey confirm growth in RF silicon designs, III-IV challenges, and trends in power-amplifier techniques.
Earlier, I reported how RF devices benefit from overall low-power mobile trends and increased digitalization. Now, a recent paper and survey reveal which digital implementation processes are gaining popularity and which specific low-power amplification techniques are favored by semiconductor intellectual-property (IP) designers.
A few months back, Globalfoundries engineers Fayyaz Singaporewala and Peter A. Rabbeni provided a Chipestimate.com Techtalk presentation entitled, “Data at the Center of RF Foundry Growth.”
In their paper, the engineers discussed the flexibility of silicon-based RF chips: “Although the Johnson limit dictates the limitation of silicon in comparison to more traditional RF technologies like III-V’s, the ability to integrate RF with digital control provides designers the capability to innovate in ways never thought of and approach or even exceed the performance of these traditional technologies (see Figure 1).
The recently completed “Chip Design Trends” (CDT) RFIC survey confirms the popularity of the silicon implementation of RF devices (see Figure 2). For current designs, more respondents listed silicon (66%) followed in order by GaAs (32%), SiGe (27%), GaN (23%), and InP (10%). For future designs, more respondents listed silicon (66%) followed in order by SiGe (31%), GaN (28%), GaAs (16%), and InP (13%). [The “Chip Design Trends” 2013 RF-MW tools survey targeted developers of products in RF and analog/mixed-signal (AMS) ICs. A total of 129 qualified designers responded to this survey.]
From both the Globalfoundries data and CDT survey, it’s clear that silicon remains a popular implementation choice for RF and microwave IC designs. Also evident from the Globalfoundries data – although not queried in the CDT survey – is that many fabs and fabless companies are looking at alternative device implementations, such as silicon-on-insulator (SOI) for both analog RF and digital apps.
Predistortion trends offered another point of comparison between the Globalfoundries paper and the CDT survey. The engineers from the foundry noted that the application of DSP concepts to RF applications is not new, “but the advancements in digital processing have reached a point where the benefits of these concepts can be efficiently realized.” Some emerging examples of these concepts include envelope tracking, tuning, and predistortion. Again, these are not new concepts, but it is only now that silicon technologies have advanced to a point which makes the application of these concepts to RF possible.
The CDT survey asked the following question: “If a discrete power amplifier (PA) is part of the RF front-end subsystem, then please rank the techniques that you would use to improve the efficiency of the PA.” As the results show (see Figure 3), digital pre-distortion is still the preferred technique for improving PA efficiency. Even though envelope tracking has received a lot of attention in the media, it ranks low in terms of priorities for PA development.
Low-power trends in high-growth areas like the mobile consumer market are driving the popularity of specific RF implementation processes and power-amplification techniques. The explosion of analog-digital smart sensor (or sensor fusion) devices should also accelerate these trends.