ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog
Visit IP Talks at DAC 2013 to learn the latest about semiconductor IP
Advertise on the world's largest semiconductor IP catalog at ChipEstimate.com Advertise on the world's largest semiconductor IP catalog at ChipEstimate.com
Advertise on the world's largest semiconductor IP catalog at ChipEstimate.com
Home  :  IP Insider  :  Article

Tag Archives: SOI Consortium

SOI Parity with CMOS Good News for IP Designers

Posted on July 13, 2012 by j.blyler@ieee.org

Share

Soitec panel at Semicon West challenges both the IDM model and the dominance of bulk CMOS as material of choice for chips at 20 nm process nodes. Continue reading →

Posted in General | Tagged , , , , , , , , , , | Leave a comment

      ChipEstimate.com Chip Planning & IP Portal -- Copyright © 2012 ChipEstimate.com. All rights reserved.
ChipEstimate.com Twitter feed  ChipEstimate.com Semiconductor IP on LinkedIn  ChipEstimate.com Semiconductor IP Channel on YouTube  ChipEstimate.com Semiconductor IP on Facebook


       Feedback  Privacy Policy  Terms of Use  Newsletter & Tech Talk Archive  IP Catalog Site Map