IP Talks at DAC 2012

Cadence IP Portal on ChipEstimate.com

Integration-optimized IP
Today's SoC designs require a new definition of IP, one that extends beyond traditional IP to address integration complexity, verification and software to significantly reduce the cost of SoC design. In this definition of IP we deliver a fully integrated IP stack that extends from the physical interface though the controller to the bare-metal software, and includes a comprehensive design and verification environment.

Component IP
Complementing Integration-Optimized IP, component IP provides both common and high-performance Silicon IP that can be utilized in many different designs. Component IP is of high quality, has a well defined set of deliverables, and works well in your SoC design environment.

Verification IP
The Cadence VIP Catalog provides support for 30+ complex protocols and 15,000+ memory device configurations. Proven on thousands of customer designs and supporting all major simulators, Cadence is your reliable one-stop shop for verification IP. Our leading-edge protocol support means you can be first to market with the latest technology. The scalable Cadence VIP supports all stages of product development including in-depth IP protocol verification, multiprotocol SoC interconnect verification, and accelerated hardware/software system verification.

 Cadence IP Search
Keywords
Node
20 nm      40 nm      55 nm      90 nm      150 nm     
28 nm      45 nm      65 nm      130 nm      180 nm     
Category
 

advertisement.gif

advertisement.gif
 

      ChipEstimate.com Chip Planning & IP Portal -- Copyright © 2012 ChipEstimate.com. All rights reserved.
ChipEstimate.com Twitter feed  Linked In account  ChipEstimate YouTube channel  ChipEstimate Facebook Page


       Feedback  Privacy Policy  Terms of Use  Newsletter & Tech Talk Archive  IP Catalog Site Map