ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog
Visit IP Talks at DAC 2013 to learn the latest about semiconductor IP

Advertise on the world's largest semiconductor IP catalog at ChipEstimate.com Advertise on the world's largest semiconductor IP catalog at ChipEstimate.com
Advertise on the world's largest semiconductor IP catalog at ChipEstimate.com

Filters / IP Cores Results

Click here for IP vendor white papers, presentations, and more -- IP Docs
 
Matching IP
38 matches found
IP Vendor IP Name Description
Altera IP-FIR FIR Compiler
Cambridge Consultants cclasicdigital1stiir DSP First Order IIR Filter
Cambridge Consultants cclasicdigital1stiir-1 DSP Frequency Discriminator
Cambridge Consultants cclasicdigital2ndhogen DSP 2nd Order Hogenauer Decimation Filter
Cambridge Consultants cclasicdigital3rdhogen DSP 3rd Order Hogenauer Decimation Filter
Cygnus SCFIR-MAX N-TAP FIR Digital Filter Core Modules Optimized For Maximum Throughput
Cygnus SCFIR-MIN N-TAP FIR Digital Filter Core Modules Optimized For Minimum Area
eInfochips eFIR-DPRAM FIR Filter - DPRAM
eInfochips eFIR-PDA FIR Filter - Parallel Distributed Architecture
LDIC LD-DV-0010-100 Continuous Time Filter.
LDIC LD-DV-0016-100 Digital Adaptive Filter
LDIC LD-RVV-CSI-0008-100 FIR
LDIC LD-RW-N-0003-100 Continuous Time Filter
MorethanIP FIR_Center FIR Center - FIR Filter Design Kit V2
NTLab 2250IP1_DIGFIL_01F2 2.56 MHz Digital filter
RF Engines DHBF001 Distributed Half Band Filter (DHBF) 1
RF Engines DHBF002 Distributed Half Band Filter (DHBF) 2
RF Engines Ventrix001 Ventrix range of high specification Pipelined Polyphase DFT cores 1
RF Engines Ventrix002 Ventrix range of high specification Pipelined Polyphase DFT cores 2
Silicon Hive HiveFlex CSP2021 32-bit C-programmable processor IP, for wireless communications signal processing, scalable from 4 to 16 parallel 16-bit MAC ope
Silicon Hive HiveFlex CSP2141 Embedded 32-bit C-programmable processor IP enables C-programmable MIMO algorithms for highest data rate mobile receivers
Synopsys Digital Signal Processing, High-Speed Digital FIR Filter High-Speed Digital FIR Filter
Synopsys Digital Signal Processing, High-Speed Digital IIR Filter High-Speed Digital IIR Filter with Static Coefficients
Synopsys Digital Signal Processing, High-Speed Digital IIR Filter High-Speed Digital IIR Filter with Dynamic Coefficients
Synopsys Digital Signal Processing, Sequential Digital FIR Filter Processor Sequential Digital FIR Filter Processor
Trilinear Technologies AVP-27 High Performance Video Scaler High performance video scaler suitable for 4Kx2K applications
Xilinx Cascaded Integrator Comb (CIC) Compiler Cascaded Integrator Comb (CIC) Compiler
Xilinx DUC/DDC Compiler DUC/DDC Compiler
Xilinx DUC/DDC Compiler DUC/DDC Compiler
Xilinx DUC/DDC Compiler DUC/DDC Compiler
Xilinx DUC/DDC Compiler DUC/DDC Compiler
Xilinx DUC/DDC Compiler DUC/DDC Compiler
Xilinx FIR Compiler FIR Compiler
Xilinx FIR Compiler FIR Compiler
Xilinx FIR Compiler FIR Compiler
Xilinx FIR Compiler FIR Compiler
Xilinx FIR Compiler FIR Compiler
Xilinx FIR Compiler FIR Compiler

Can't find what you're looking for? Our IP Concierge service can help, click here.


Related IP Docs  Related IP Docs!
 Verifying the LIN automotive network (IP Doc by Cadence)
 Simple Ways to Manage Different Clock Frequencies of Audio Codecs (IP Doc by Synopsys)
 Sweet Sounding SoCs: Why Analog Audio IP Lowers Costs and Sounds Better than Digital PWM (IP Doc by Synopsys)
 Understanding Clock Jitter Effects on Data Converter Performance and How to Minimize Them (IP Doc by Synopsys)
 Demystifying Non-volatile Memory IP (IP Doc by Synopsys)
 Cadence SoC Realization (IP Doc by Cadence)
 Reality Check: A Guide to Understanding Optimized Processor Cores (IP Doc by Synopsys)
 Addressing Power and Speed Requirements of Mobile Devices with Data Converter IP (IP Doc by Synopsys)
 Shrinking SoC Design Cycles Using DesignWare Intellectual Property (IP Doc by Synopsys)
 Protect Your Electronic Wallet Against Hackers (IP Doc by Synopsys)
 Unleash the Performance Benefits of Sigma-Delta ADCs into Your SoC (IP Doc by Synopsys)
 Simulating FPGA Power Integrity Using S-Parameter Models (IP Doc by Xilinx)
 The Xilinx Isolation Design Flow for Fault-Tolerant Systems (IP Doc by Xilinx)
 High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs (IP Doc by Xilinx)
 Xilinx Redefines Power, Performance, and Design Productivity with Three Innovative 28 nm FPGA Families: Virtex-7, Kintex-7, and Artix-7 Devices (IP Doc by Xilinx)
 Considerations Surrounding Single Event Effects in FPGAs,ASICs, and Processors (IP Doc by Xilinx)
 Practical Use of FPGAs and IP in DO-254 Compliant Systems (IP Doc by Xilinx)
 DO-254 for the FPGA Designer (IP Doc by Xilinx)
 Partial Reconfiguration of Xilinx FPGAs Using ISE Design Suite (IP Doc by Xilinx)
 Lowering Power at 28 nm with Xilinx 7 Series FPGAs (IP Doc by Xilinx)
 High-Volume Spartan-6 FPGAs: Performance and Power Leadership by Design (IP Doc by Xilinx)
 Improving Performance in Spartan-6 FPGA Designs (IP Doc by Xilinx)
 Reducing Switching Power with Intelligent Clock Gating (IP Doc by Xilinx)
 Increased Productivity Using Team Design (IP Doc by Xilinx)
 Hierarchical Design Using Synopsys and Xilinx FPGAs (IP Doc by Xilinx)
 Virtex-6 FPGA Routing Optimization Design Techniques (IP Doc by Xilinx)
 Audio Subsystems for Efficient SoC Integration: Integrating High-Definition Multi-Channel Audio Solutions at the Speed of Sound (IP Doc by Synopsys)
 High-End Audio Made Easy: The Software Story: Software Integration of an Audio Subsystem into a System on Chip (IP Doc by Synopsys)
 Technical Considerations for Implementing USB 3.0 on SoCs (IP Doc by Synopsys)
 Mixed-Signal IP Design Challenges in 28-nm Process and Beyond (IP Doc by Synopsys)
 Implementing Audio Codecs in 28-nm Mobile Multimedia Advanced SoCs (IP Doc by Synopsys)
 

 Filter DSP IP implements fundamental DSP algorithms, such as Fast Fourier Transforms (FFT) and FIR (Finite Impluse Response) filters






     Language: Search for Semiconductor Design and Verification IP at ChipEstimate.com English | Search for Semiconductor Design and Verification IP at ChipEstimate.jp Japanese | Search for Semiconductor Design and Verification IP at ChipEstimate.cn Chinese
 
      ChipEstimate.com Chip Planning & IP Portal -- Copyright © 2013 ChipEstimate.com. All rights reserved.
ChipEstimate.com Twitter feed  ChipEstimate.com Semiconductor IP on LinkedIn  ChipEstimate.com Semiconductor IP Channel on YouTube  ChipEstimate.com Semiconductor IP on Facebook  ChipEstimate.com Semiconductor IP on Google+ 


       Feedback  Privacy Policy  Terms of Use  Newsletter & Tech Talk Archive  IP Catalog Site Map