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CoreConnect / IP Cores Results

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Browse   :  On-Chip Bus IP  :  CoreConnect
Matching IP
12 matches found
IP Vendor IP Name Description
Xilinx AHB-Lite to AXI Bridge AHB-Lite to AXI Bridge
Xilinx AXI Quad SPI AXI Quad SPI
Xilinx CoreConnect Technology CoreConnect Technology
Xilinx CoreConnect Technology CoreConnect Technology
Xilinx CoreConnect Technology CoreConnect Technology
Xilinx CoreConnect Technology CoreConnect Technology
Xilinx CoreConnect Technology CoreConnect Technology
Xilinx DCR Bus Structure DCR Bus Structure
Xilinx Fabric Co-processor Bus V2.0 (FCB) Fabric Co-processor Bus V2.0 (FCB)
Xilinx OPB to DCR Bridge OPB to DCR Bridge
Xilinx OPB to PLB Bridge OPB to PLB Bridge
Xilinx PLB Bus Structure PLB Bus Structure

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Related IP Docs  Related IP Docs!
 Simulating FPGA Power Integrity Using S-Parameter Models (IP Doc by Xilinx)
 The Xilinx Isolation Design Flow for Fault-Tolerant Systems (IP Doc by Xilinx)
 High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs (IP Doc by Xilinx)
 Xilinx Redefines Power, Performance, and Design Productivity with Three Innovative 28 nm FPGA Families: Virtex-7, Kintex-7, and Artix-7 Devices (IP Doc by Xilinx)
 Considerations Surrounding Single Event Effects in FPGAs,ASICs, and Processors (IP Doc by Xilinx)
 Practical Use of FPGAs and IP in DO-254 Compliant Systems (IP Doc by Xilinx)
 DO-254 for the FPGA Designer (IP Doc by Xilinx)
 Partial Reconfiguration of Xilinx FPGAs Using ISE Design Suite (IP Doc by Xilinx)
 Lowering Power at 28 nm with Xilinx 7 Series FPGAs (IP Doc by Xilinx)
 High-Volume Spartan-6 FPGAs: Performance and Power Leadership by Design (IP Doc by Xilinx)
 Improving Performance in Spartan-6 FPGA Designs (IP Doc by Xilinx)
 Reducing Switching Power with Intelligent Clock Gating (IP Doc by Xilinx)
 Increased Productivity Using Team Design (IP Doc by Xilinx)
 Hierarchical Design Using Synopsys and Xilinx FPGAs (IP Doc by Xilinx)
 Virtex-6 FPGA Routing Optimization Design Techniques (IP Doc by Xilinx)
 

 CoreConnect is a microprocessor bus architecture for system-on-a-chip (SoC) designs.

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