400Mb/s DDR DLL
600Mb/s DDR DLL Macro
700 Mbs DDR DLL
800 Mbs DDR DLL
Mobile DDR DLL
800Mb/s DDR DLL
mDDR Pad Set (Designed for Common Platform 90LP)
mDDR Pad Set (Designed for Common Platform 65G)
mDDR Pad Set (Designed for Common Platform 90G)
mDDR Pad Set (Designed for Common Platform 65LP)
DDR2, DDR controller. Highly efficient interleaving for maximum bus efficiency. AHB/APB or Wishbone bus interface.
DDR DLL PHY 32bit (supports up to DDR1066)
DDR Hardened 8-bit data/address/control Slice for DDR DLL PHY (must be combined with IO's and ESD) - supports up to DDR1066
DDR Memory Controller IP for DDR1, DDR2, DDR3, DDR4, LPDDR1, LPDDR2, WideIO
Hard PHY - DDR2 / LPDDR2 / DDR1 DLL PHY - TSMC65LP
DDR2/DDR1 Combination Memory Controller IP
DDR3/DDR2 Combination Memory Controller IP
DDR4/DDR3 Combination Memory Controller IP
LPDDR1 Memory Controller IP
Hard PHY - LPDDR2 / DDR3 / DDR3L DLL PHY - TSMC28HPM
Hard PHY - LPDDR2 / DDR3 / DDR3L DLL PHY - TSMC28HPM - pre-implemented 16-bit PHY
Hard PHY - LPDDR2 / DDR2 / DDR3 / DDR3L DLL PHY - TSMC40LP
Hard PHY - LPDDR2 / DDR2 / DDR3 DLL PHY - TSMC40LP - pre-implemented 32-bit PHY
Hard PHY - LPDDR2 / DDR3 / DDR3L DLL PHY - TSMC40G
LPDDR2 Memory Controller IP
LPDDR2/LPDDR1 Combination Memory Controller IP
LPDDR2/LPDDR1 NVM Combination Memory Controller IP
Hard PHY - LPDDR3 / LPDDR2 DLL PHY - TSMC28HPM
LPDDR3 Memory Controller IP
LPDDR3/LPDDR2 Combination Memory Controller IP
LPDDR3/LPDDR2/LPDDR1 Combination Memory Controller IP
Wide-IO Memory Controller IP
DDR2 PHY Interface Layer
DDR2/3 combo PHY
DDR2 Verification IP in SystemVerilog(OVM/VMM) and Verilog
DDR3 nVS in SystemVerilog (UVM/OVM/VMM) and Verilog
DDR3 Memory Controller