Chip Planning Portal Overview
Free registration at allows you to download a complimentary copy of the InCyte Chip Estimator Starter Edition. Click on the link below to download your copy now or to learn more about advanced chip planning and IP re-use products from Cadence Design Systems.

InCyte Chip Estimator Starter Edition is the free downloadable, entry-level system used for project feasibility analysis at the early architectural stage of chip planning. The tools bases estimates on industry average IP library and process models, providing early predictions of chip die size, power, and leakage.Results are generally accurate enough for very rough analysis but should not be used for production IC designs or as the basis for technical or economic decisions. Learn more ...

Cadence InCyte Chip Estimator is a production quality, silicon provide accurate chip estimation and planning system from Cadence Design Systems. It is used to develop and refine chip specifications, manage die and packaged chip costs, and aid in the exploration of various IP and manufacturing options. InCyte Chip Estimator estimates are based on technology models created from design kits provided by leading IP suppliers and semiconductor manufacturers for increased accuracy. The tool guides users in the what-if analysis process, optimizing their specifications to achieve functionality and performance goals. In addition to die size, power, and leakage estimates, InCyte Chip Estimator allows users to input and assess performance targets and leverage available connectivity data for the most realistic chip estimation possible.
The system also includes the ability to use block diagrams as part of the specification input, and assists users in finding the IP that meets their functional and performance requirements. Rapid what-if analysis enables quick iterations to compare and refine design plans to achieve the optimal balance of functionality, performance and cost. Comprehensive technical reports and chip budgetary quotes are generated and direct integration into leading EDA implementation tools enables convergence from initial design estimations to final silicon. Learn more ...

Cadence Chip Planning System offers a complete and customizable chip planning and IP re-use solution for semiconductor and electronic systems companies. The solution is used to generate refined chip specifications, accurate IC quotations and to customize chip estimations to meet their corporation's internal requirements. The Chip Planning System allows for estimation with custom IP and manufacturing processes and for tuning of technology models for the highest possible accuracy. The system resides within a customer's secure corporate network, providing users with a local, dedicated chip estimation environment. The Chip Planning System can be linked into internal IP and technology databases and tightly integrated into a company's chip implementation flow. Learn more ...


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