Chip Planning Overview
InCyte provides a complete cockpit for early chip planning enabling accurate estimation and rapid what-if analysis. The system aids design teams in optimizing a chip specification that maximizes performance while optimizing die size, power and cost. InCyte is leveraged from the earliest phases of the chip design cycle for early technical and economic chip feasibility analysis and exploring the impact of various IP choices, manufacturing nodes and a variety of chip architecture options. The system is also utilized throughout the chip implementation flow for rapid what-if analysis that would otherwise be time consuming in traditional implementation tools.
Die size, performance, power, leakage, yield and production chip cost are estimated, and package recommendations are provided. InCyte has been correlated for accuracy to within 98% of silicon, as estimates are based on actual semiconductor manufacturer and IP vendor technology models. InCyte predicts the following key IC metrics:
Die area - Total die size and bounding, factoring in all specified IP and design components, including optional connectivity.
Performance - Feasibility of achieving user-specified performance targets and guidance on IP library selection.
Power - Dynamic power consumption across various functional states of the chip.
Leakage - Static power consumption across various functional states of the chip.
Yield - Based upon industry or user-defined logic and memory defect density data, cumulative chip yield is calculated.
Cost - Production chip cost calculated utilizing customizable industry wafer pricing, test & assembly, package, and mask cost data.
Predicting A Chip Design
Integrating InCyte into a chip planning process is easy, and the input required is minimal. Whether you are at the inception of a new chip design or looking to evaluate tradeoffs midstream, InCyte can be leveraged for rapid what-if analysis. Specifications of gate count, memory size, number of I/Os and IP blocks are used to generate an estimate that can be used to assess the technical and economic viability of a design. Users may input design data visually with a block diagram or in a simple table format. Performance targets and connectivity information can be also be added to obtain a more complete estimation. InCyte includes a comprehensive IP catalog from which users can select technology nodes, process variants and IP macros under consideration. Users can also import IP lists they generate while searching and selecting IP online within the ChipEstimate.com catalog.
Since InCyte utilizes technology models that are generated from the same design kit data used by chip implementation tools, results correlate well with final silicon. Once an initial estimation is performed, users can perform rapid what-if analysis to compare their design across technology nodes, processes, IP options, and varying chip specifications - all in a matter of seconds.
InCyte Features
Accurate chip size, power, performance and cost estimation
Rapid architectural level what-if analysis
Profile based power and leakage estimation
Block diagramming and connectivity definition
Automatic early floorplan creation and editing
IP library selection guidance and performance analysis
Package recommendations and industry pricing
Comprehensive chip economic analysis
Bundled support for thousands of IP and manufacturing technologies
Supported Manufacturers and IP Library Vendors
InCyte enables accurate chip estimations specific to processes and IP libraries from leading third party semiconductor manufacturers and IP vendors. Models for hundreds of process technologies and IP libraries are bundled with InCyte. Supported foundries and IP library vendors are provided in the list below. Additional manufacturers and vendors are available upon request.
IP Library Vendors: ARM (Artisan), Faraday, MOSAID, Synopsys, TSMC, Virage Logic
Note: Custom manufacturing processes and IP libraries are supported in InCyte Enterprise.
Cost Aware Design
InCyte enables cost awareness at the earliest phases of the design cycle, when it can be leveraged most. Design teams can now optimization design specifications earlier in the design flow, factoring in cost at the same time as performance and functionality are considered. InCyte's economic analysis delivers a complete budgetary quote, reporting on all factors contributing to production chip cost. An extensive database of package options is included, enabling InCyte to recommend a package based on technical estimation results and to predict volume-based package pricing. Silicon wafer pricing and defect density data allow systematic yield analysis providing 'good die' cost. InCyte's analysis of design components predicts test & assembly costs, while industry non recurring engineering (NRE) costing data provides process specific mask cost estimations.
To ensure the most current economic data is used in predictions, industry wafer pricing, defect data, and packaging data are automatically updated quarterly. The economic models that drive the calculation engine are user-customizable, allowing users to tailor estimations to meet their needs.
Lifecycle analysis is used to forecast chip cost over time, taking into account decreasing wafer costs, improving defect densities and other parameters. Return on investment (ROI) analysis enables users to understand over what timeframe and volume non-recurring engineering costs may be amortized and profitability on a design may be achieved.
Drive Results Into Silicon
Estimation results are output in various user selected formats including charts, reports, and tables describing die area usage, chip bounding, dynamic and static power consumptions, yield, and production chip cost. A preliminary chip floorplan is also generated and can be edited to communicate physical design intent. Budgetary quotations providing a comprehensive breakdown of production chip cost are also provided. Users may export all technical and economic estimation results in Microsoft Excel format or in a user-definable custom report.
InCyte provides direct integration into leading EDA implementation flows from Cadence, Magma, Mentor Graphics and Synopsys. Design specification, IP, constraints and floorplan data may be exported in industry standard files formats to drive InCyte results directly into the chip implementation flow. The integrated Design Export Wizard provides an easy yet powerful interface to dynamically generate tool scripts and export design data for direct import into synthesis and floorplanning tools.
To get started with InCyte, click here to learn more about pricing and availability.
