InCyte Chip Estimator Starter Edition is the free downloadable, entry-level system used for project feasibility analysis at the early architectural stage of chip planning. The tools bases estimates on industry average IP library and process models, providing early predictions of chip die size, power, and leakage. Results are generally accurate enough for very rough analysis but should not be used for production IC designs or as the basis for technical or economic decisions.
InCyte Chip Estimator Starter Edition Features
InCyte Chip Estimator Starter Edition is freely available to registered users of ChipEstimate.com. The system is used by thousands of electronics companies to assess project feasibility, compare different IP, chip architecture and manufacturing processes and their impact on die size and power consumption. Users input a high level design specification and the InCyte Chip Estimator Starter Edition produces industry average estimations of chip die size, power, and leakage. Models used for estimation are built based upon averages from leading foundries and IP library suppliers, and while results will provide rough accuracy, they should not be used on production IC designs or as a basis for critical decision making. InCyte provides industry average estimation of the following key metrics:
Using the InCyte Chip Estimator Starter Edition
Integrating the InCyte Chip Estimator Starter Edition into a chip planning process is easy, and input required is minimal. Specifications of gate count, memory size, number of I/Os and IP blocks are the basic inputs required to generate an estimate that can be used to assess the feasibility of a design. InCyte Chip Estimator Starter Edition includes a comprehensive IP catalog from which users can select technology nodes, process variants and IP macros under consideration. Users can also import IP lists they generate while searching and selecting IP on the ChipEstimate.com portal. InCyte Chip Estimator Starter Edition uses the user-selected IP to calculate die size, power and leakage based on industry average foundry and IP library models.
Estimation results are presented in comprehensive datasheets as well as visualizations and graphs. An early floorplan visualization is also generated.
Enhanced Accuracy, Chip Cost Estimation and More...
Need more accurate estimates which are specific to foundries, ASIC vendors, and internal or external IP library providers?
Would you like to estimate production chip cost factoring in package recommendations, wafer pricing, defect density data, and non-recurring engineering costs?
Would you like to perform what-if analysis across various low power techniques and converge on your estimates through a tight link to leading IC implementation tools?
What do all of these things have in common? They were key topics addressed by Cadence...