Comprehensive Chip Planning
InCyte Enterprise is an extensive and customizable environment designed for chip-level architectural planning and specification capture. Using technical and economic data models from across the semiconductor design chain, chip die size, performance, power, leakage, yield and cost are accurately estimated at the earliest stages of the design flow. Design teams use InCyte Enterprise as their cockpit to capture and optimize chip specifications, perform rapid what-if analysis and to drive chip architecture plans into EDA flows to guide downstream implementation tools.
InCyte Enterprise Features
Accurate chip size, power, performance and cost estimation
Rapid architectural level what-if analysis
Profile based power and leakage estimation
Block diagramming and connectivity definition
Automatic early floorplan creation and editing
IP library selection guidance and performance analysis
Custom package support
Tailored chip economic analysis
Support for custom process technologies
Support for custom IP libraries and memory technologies
Estimation tuning for the highest degree of silicon correlation
InCyte Enterprise couples sophisticated estimation algorithms and technology models with an easy to use interface providing extensive chip planning capabilities with ease of use. Chip architects, design leads, management, and other teams involved in chip projects - even those without extensive IC implementation knowledge - rely on InCyte Enterprise to assemble and evaluate chip specifications and to optimize architectures for higher performance, lower overall cost and reduced power consumption. The system enables users to provide better chip plans to guide traditional EDA design flows.
The system combines a user's high-level design intent with embedded design rules and IP, process and economic data models to produce accurate estimates. Side-by-side comparison of specifications under consideration can be performed, and the system can pass design and technology data directly into leading EDA floorplanning tools enabling convergence from initial specification to final silicon.
Estimates are based on configurable models tuned to internal or external manufacturing technologies IP libraries. InCyte Enterprise has been proven to deliver results that correlate to within 98% of silicon. The tool estimates the following key metrics.
Die area - Total die size and bounding, factoring in all specified IP and design components, including optional connectivity.
Performance - Feasibility of achieving user-specified performance targets and guidance on IP library selection.
Power - Dynamic power consumption across various functional states of the chip.
Leakage - Static power consumption across various functional states of the chip.
Yield - Based upon customizable defect density data, cumulative chip yield is estimated.
Cost - Production chip cost calculated utilizing customizable wafer pricing, test & assembly, package, and mask cost data.
Leveraging InCyte Enterprise
Integrating InCyte Enterprise into an existing chip planning process is easy, and the input required is minimal. Whether you are at the inception of a new chip design or looking to evaluate tradeoffs midstream, InCyte can be leveraged for rapid what-if analysis. Specifications of gate count, memory size, number of I/Os and IP blocks are used to generate an estimate that can be used to assess the technical and economic viability of a design. Users may input design data visually with a block diagram or in a simple table format. Performance targets and connectivity information can be also be added to obtain a more complete estimation. Drawing on the integrated IP catalog or an internal corporate catalog, InCyte Enterprise users can select technology nodes, process variants and IP macros under consideration. Users can also import IP lists they generate while searching and selecting IP in the ChipEstimate.com IP catalog. InCyte Enterprise utilizes technology models either provided by ChipEstimate.com or produced with the optional Technology Macro Modeler software.
The system also features a quick estimation wizard that further simplifies the steps to produce accurate estimations of chip size, power, and cost, so users with only cursory knowledge of specification data can generate results. These early system-level chip viability assessments can then be refined over time for even greater accuracy as a chip's specification evolves. With InCyte Enterprise's integrated design rules and technology models, design architects can now marry early specifications directly to real implementation data without the complexity of implementation tools.
Size, Performance, Power and Cost Optimization - RTL Not Required
Once a chip specification has been captured, InCyte Enterprise provides an environment for users to perform rapid what-if analysis to compare and optimize their design architectures. Users can compare their design across manufacturing options such as varying technology nodes and process variants, IP options such as varying IP libraries, memory configurations, and digital and analog IP cores, and chip architectures such as utilizing clock gating, multiple voltage domains, and different packaging options to ultimately reduce chip size, power and cost.
Results are generated in seconds; users can perform side-by-side comparisons of a design with different specifications to visualize tradeoffs between die size, power, leakage, yield, cost and other parameters and to ultimately converge upon an optimized chip specification.
InCyte Enterprise's power profile analysis enables architectural-level planning for chip dynamic and static power across different functional modes of the device. In a wireless handset chip for example, estimations include power across different states of the chip such as a "talk" versus "standby" mode, enabling visibility into how chip architecture, IP and packaging options will affect overall performance and cost. InCyte doesn't require RTL or simulation vectors, so performance and power analyses can be started at the earliest stages in the design flow. Before RTL is written is when this feedback is leveraged most effectively to determine chip viability and ultimately reduce final system costs - and wasted design iterations.
Economic Analysis - Packaged Chip Cost
InCyte Enterprise's analysis provides immediate economic feedback on chip plans, producing a quantifiable measure of the economic ramifications of chip technical specifications. Building on technical estimation results, the comprehensive analysis factors in customizable economic data to provide users with an accurate estimation of production chip cost. InCyte Enterprise recommends a package based on technical estimation results and provides an estimate of volume-based pricing. The package database may be provided internally or by a 3rd party vendor in industry standard XML format.
Customizable silicon wafer pricing, logic and memory defect densities, test & assembly costs, and non-recurring engineering costs are factored in to produce a final packaged chip cost estimation including a detailed and customizable budgetary report. Economic models which drive the calculation engines are fully customizable.
InCyte users have the option of performing a lifecycle analysis to forecast chip cost over time, taking into account decreasing wafer costs, defect densities and other parameters. Return on investment (ROI) analysis enables users to understand over what timeframe and volume non-recurring engineering costs may be amortized and profitability on a design may be achieved.
Encapsulated Semiconductor Ecosystem
InCyte Enterprise includes comprehensive and fully integrated IP, manufacturing data, design rules, and economic models to enable users with diverse experience levels to generate accurate chip estimations. Using the same data that is typically only utilized later during EDA implementation flows enables the highest degree of accuracy at the architectural stage. The system encapsulates IP libraries, process technologies, bonding styles and other design kit data so that high-level chip specifications can be mapped into a realistic physical implementation - without the complexity, time and skill-set required to run implementation tools.
Working with over 175 IP suppliers and foundries, the integrated ChipEstimate.com catalog contains thousands of IP components, cell and memory libraries and foundry process technology models enabling the most accurate chip estimation possible. Users can leverage both internal IP and process models as well as draw on the ChipEstimate.com catalog from directly within the tool.
Automated Technology Modeling for Internal IP
InCyte Enterprise offers an optional Technology Macro Modeler (TMM) tool which characterizes IP and process design kit data for use in estimation. TMM reads customer-provided industry standard design kits and from them produces a set of macro models that are used by InCyte Enterprise as the foundation for accurate chip estimation. Technology models are built from the same IP and process data used by industry leading EDA implementation tool flows ensuring a tight correlation to final silicon.
IP Catalog Management
InCyte Enterprise is a complete client-server-based solution which can be deployed behind your corporate firewall. The system utilizes an "auto-update" feature to ensure that users are always estimating with the latest IP, process, and economic models which are kept up to date on the InCyte Enterprise Server. The InCyte Enterprise server includes a comprehensive IP catalog management system, providing a web-based interface for users to manage their integrated IP catalog. InCyte Enterprise can be configured to synchronize directly with internal IP catalog systems to provide seamless integration with existing IP databases.
Drive Results Into Silicon
Chip estimation results are output in various user selected formats including charts, reports, and tables describing all technical and economic estimation results. InCyte Enterprise also automatically produces to scale physical chip visualizations. Floorplan editing functionality provides the means for users to communicate their design intent in a visual, to scale physical form. Allowing downstream teams to see how chip architects have visualized IP and subsystem placement intent reduces the occurrence of costly design mistakes.
Budgetary quotations providing a breakdown of production chip cost are also produced. Users may export all technical and economic estimation results in Microsoft Excel, PDF and a variety of other reporting formats. A comprehensive custom report generation system is also provided to produce virtually any report format out of InCyte Enterprise.
The system also provides direct integration into leading EDA implementation flows from Cadence, Magma, Mentor Graphics and Synopsys. Design specification, IP, constraints and floorplan data may be exported in industry standard files formats to drive InCyte Enterprise results directly into the chip implementation flow. The Integrated Design Export Wizard provides an easy yet powerful interface to dynamically generate tool scripts and export design data for direct import into synthesis and floorplanning tools.
