November 2, 2010

	Mixed Signal IP for Precision Distance Measurement   Vijay Srinivas Syed S. Islam Alvand Technologies Traditionally, distance measurement has always been related to the RF domain. Today many complicated SoCs have been designed to include mixed-signal base-band and digital domain functionalities for high precision distance measurement. Due to a very compact silicon area, standard CMOS fabrication procedure and significantly reduced on-board component (BOM) cost, this SoC has a huge potential and value. One of the biggest challenges in this SoC is the front end receive path Analog-to-Digital Converter (ADC). The system requirements are very stringent due to high bandwidth requirement and high sampling speed. more >> AuthenTec’s SafeXcel-IP-proven security IP for SoC, ASIC, and FPGA designs. more >>		SATA-3 Dev/Host, USB-3, USB-2, Reed Solomon, ATA-7 Dev/Host, AES 128-256 more >> USB 3.0 SuperSpeed Device Controller compliant with USB3.0... from Innovative Logic USB2.0 IP is a HS_FS USB controller, OTG capable, dual role usb2_0... from Innovative Logic OTP- High Density (8K-256K) with 70% Smaller Footprint from Novocell Semiconductor 2x or 4x write Antifuse OTP/MTP-128x8-NVM Memory IP from Novocell Semiconductor OTP/eMTP: 16 Kbit NVM in 90nm Standard Logic CMOS process from Sidense OTP/eMTP: 32 Kbit NVM in 65nm Standard Logic CMOS process from Sidense PLL-Low Noise Programmable PLL from S3 Group The AMBIST fully autonomous on-chip self-test for verification by YFL Elite. Power On Reset Circuit from S3 Group 256-bit SHA Cryptoprocessor Core from CAST Data Encryption Standard Core from CAST USB 3.0 nVS in SystemVerilog (UVM/OVM/VMM) and Verilog from nSys One-Time-Programmable (OTP) NVM solutions for boot code and... from Kilopass Technology One-Time-Programmable (OTP) NVM solutions for micro code... from Kilopass Technology Few time programmable CMOS based NVM targeted at trim... from Synopsys (formerly Virage Logic... Few time programmable CMOS based NVM targeted at trim... from Synopsys (formerly Virage Logic... 16-Bit Sigma-Delta ADC from MOSCAD Design & Automation High Power Line Driver from MOSCAD Design & Automation		ChipEstimate.com is your resource for all things IP   Discover the latest white papers from top IP Providers on ChipEstimate.com. Explore IP Docs! to access dozens of technical papers from industry leaders such as Mosys, Cadence, Tensilica, Eureka, Synopsys, Sidense and more. Download white papers now! Encryption & Compression   The Fastest Verification   We make things visibleTM Ultra Low Power DSP Core
	Multi-bank, density optimized eDRAM from IBM Serializer/Deserializer supporting RapidIO 2.1 communication protocol from HDL Design House H.264/AVC HD & ED Video Encoder Core from CAST High Density Standard Cell Library from ARM AES Encryption/Decryption Core from Catena 4 - 256MHz High Precision RC Oscillator from MOSCAD Design & Automation One-Time-Programmable (OTP) NVM solutions for micro code... from Kilopass Technology USB 3.0 SuperSpeed Device Controller compliant with USB3.0... from Innovative Logic 12-bit 2MS/s Dual Input ADC with Temperature Sensor from S3 Group
	ARM Techcon is Next Week! Receive a 50% Savings or sample the content with your FREE one class pass. Learn more. Immerse yourself in the design strategies and solutions for ARM. Register Now with Promo Code ARM50. more >>
	RFaxis Achieves the Impossible and Samples Its Breakthrough Pure CMOS... RFaxis Samples the World's First and Only Single-Chip/Single-Die RF Front-end ICs Manufactured on Standard Pure CMOS Silicon at Multiple Foundries Open-Silicon Expands Presence in India With New SoC and Systems... Additional Global Facility Meets Increasing Demand for Derivative SoC Solutions BANGALORE, India, Nov. 1, 2010 - (PRNewswire) - Open-S Free Software Enables Development of IEEE 1149.1-2011 JTAG and IJTAG... DOVER, NH -- (MARKET WIRE) -- Oct 29, 2010 -- Intellitech announced today a free version of its NEBULA software to enable FPGA and SoC designers BEEcube Announces the BEE4-W, with Integrated High-speed ADC/DAC... The Ultimate Full Speed Mixed Signal FPGA Based Prototyping Platform Now Targets Aerospace, Defense and Wireless Applications FREMONT, Calif., Nov. Emerson Network Power and Mercury Computer... SAN JOSE, Calif.--(BUSINESS WIRE)--Emerson Network Power and Mercury Computer Systems announced today that they will collaborate to promote interoperability on... X-ES Introduces the Avionics Development... MIDDLETON, WI--(Marketwire - November 1, 2010) - Extreme Engineering Solutions, Inc. (X-ES) is shipping the Avionics Development Platform (ADP) to facilitate the... AML Communications Schedules Second Quarter... CAMARILLO, Calif.--(BUSINESS WIRE)--AML Communications, Inc. (OTCBB:AMLJ), a designer, manufacturer and marketer of microelectronic assemblies... Mentor Graphics and ARM Join Forces on Memory Test and Repair WILSONVILLE, OR--(Marketwire - November 1, 2010) - Mentor Graphics Corporation (NASDAQ: MENT) today announced it has teamed up with ARM to provide an... The Consortium for IT Software Quality (CISQ) Launches "IT Software... Downloadable Audio Discussions Focus on IT Software Quality and Measurement With Leading Executives Across Multiple Industries Overture Extends MaestrOS Service Engine to First Carrier Ethernet Edge... RESEARCH TRIANGLE PARK, N.C.--(BUSINESS WIRE)--Overture Networks introduces the ISG 400 Carrier Ethernet edge platform in order to dramatically simplify the... CEVA Partners with eyeSight to Offer Hand Gesture Recognition Solution... CEVA and eyeSight to demonstrate the technology live at CEVA DSP Technology Symposium in Tokyo, Japan, November 8 ... Synopsys Expands Synthesis-Based Test Technology to Increase Designer... Unveils Plan to Accelerate Implementation of Higher Quality, Lower Cost Test MOUNTAIN VIEW, Calif., Nov. 1, 2010 (PRNewswire) Syno Ricoh Adopts DeFacTo HiDFT-SIGNOFF Solution for Digital IC Design for Test Grenoble, France, November 1st. DeFacTo Technologies S.A. today announced that Ricoh Company Ltd. has started to adopt DeFacTo HiD
	True Circuits New General Purpose PLL Hard Macros The General Purpose PLL is a wide range clock multiplier with deskew capability that is ideal for low power, area sensitive and low cost applications. It is available in TSMC and GlobalFoundries processes from 130nm to 28nm. Visit the timing experts today. Click here now! more >>
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