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Using 1T-OTP in FPGAs and other Reconfigurable Logic
Eddy Huang
and Jim Lipman
Sidense Corp. |
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Introduction
Driven by the demands of the consumer electronics marketplace - low price points and constantly shrinking design cycles - programmable logic and reconfigurable silicon solutions are rapidly gaining acceptance by chip designers for a wide range of product development. Being able to accelerate code development on a completed hardware platform and to reconfigure logic on a chip to handle different computational requirements are just two of the reasons designers are using reconfigurable hardware in their products.
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GLOBALFOUNDRIES - first foundry with HKMG in high volume production today. more >>
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Need OTP with low READ and programming voltages? NSCore is the OTP for you. more >> |
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OTP-64bit Serial in 180nm NVM Memory IP, STD CMOS, for...
from Novocell Semiconductor |
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OTP- High Density (8K-256K) with 70% Smaller Footprint
from Novocell Semiconductor |
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OTP/eMTP: 256 Kbit NVM in 65nm Standard Logic CMOS process
from Sidense |
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OTP/eMTP: Ultra low power 256 bit NVM in 180nm Standard Logic...
from Sidense |
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100 MHz on chip Filter delivers channel selection and down...
from Kaben Wireless |
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Multi Gigabit Ethernet Switching, Routing with QoS ,Packet...
from Posedge Inc. |
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100G, 19.25% OH, 10dB or higher NECG CI-BCH-4 eFEC...
from Vitesse Semiconductor |
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100G, 7% OH, 9.35dB NECG CI-BCH-3 eFEC Encoder/Decoder
from Vitesse Semiconductor |
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144 MHz DLL delivers low phase noise
from Kaben Wireless |
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ADC family uses all digital library cells with no analog block...
from Stellamar |
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10 bit 100 kHz bandwidth Digitally synthesizable ADC for FPGA/ASIC
from Stellamar |
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MUSBHSFC core provides a USB function controller that has been...
from Innovative Logic |
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Wireless USB Device Controller compilant to spec 1.0 supporting...
from Innovative Logic |
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Fully autonomous on-chip self-test/verification and chip...
from YFL Elite |
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PCIe PHY, SMIC 65LL, x1
from Synopsys |
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SD4.0 UHS-II PHY
from Silicon Library |
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See IP Talks! at DAC 2011 |
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Meet with the world's leading IP Suppliers. Learn about the latest in IP with IP Talks!
Don't miss your
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Booth 1731.
Participants will be entered to win an iPod, Bose headset or Canon DSLR camera!
Visit us for a sneak preview now! |
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Design IP
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Leading Innovation to Chip.
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PCI Express
Verification IP |
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Ultra Low Power DSP Core
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Introducing NovoBits: 8-256 bit antifuse memory blocks targeted at polyfuse replacement.
NovoBits offers a drop-in solution that can be easily ported within an existing design. more >>
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CVD Equipment Corporation Announces Exercise of Over-Allotment Option...
RONKONKOMA, N.Y. - CVD Equipment Corporation (Nasdaq: CVV) today announced that the underwriter of its public offering of common stock which was...
NetLogic Microsystems Selects Helic's Tools for RF IC Design Flow
SAN FRANCISCO, May 27, 2011 - Helic, Inc., the technology leader in EDA solutions for RF and high-speed IC design proudly announces that NetLogic...
Smart Grid sensitized by Dolphin Integration with high resolution and...
Grenoble, France - May 27, 2011 - Power metering is a key function in smart grids, enabling a precise control of power consumption for ecological and economic...
Open-Silicon Introduces "On Time, or On Us" Program
New Program Raises the Industry Bar on Schedule Predictability MILPITAS, Calif., May 27, 2011 - Open-Silicon, Inc., a leading...
IME AND TOWERJAZZ COMBINE EXPERTISE TO ACCELERATE MEMS DEVICE...
Singapore, 25 May 2011 - The Institute of Microelectronics (IME), an institute of the Agency for Science, Technology and Research (A*STAR) have...
More than Moore and E-Mobility at DATE 2012 in Dresden
Dresden, Germany - May 26, 2011 - As DATE's new concept of choosing the vibrant European clusters Dresden (2010) and Grenoble (2011) as new venues...
Silicon Frontline Addresses EDA Industry Bottleneck, Promotes...
SAN DIEGO, CA - May 25, 2011 - Who/What Silicon Frontline Technology, Inc. (SFT), an Electronic Design Automation (EDA) company, in...
Cadence U.S. Patents Top 1,000
Two Decades of Design Innovation Make Cadence the Patent Leader in EDA SAN JOSE, Calif., 26 May 2011 Cadence Design...
Synopsys Delivers 28-nm Design Solutions and Advanced System-Level...
Flow provides optimized methodologies to shorten time-to-market and time-to-volume for designers using TSMC's 28-nanometer process technology...
Skyworks to Acquire Power Management Innovator Advanced Analogic...
Expands Portfolio with Leading Edge Analog Products and Accelerates Entry into Adjacent Vertical Markets; Immediately Accretive Post-Closing...
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PLDA introduces the first low profile FPGA prototyping board featuring dual-10G Ethernet and PCI Express Gen3:
- Based on Altera Stratix IV GX
- Supports PCIe Gen2 and Gen3
- Dual 10 Gigabit Ethernet interfaces (SFP+)
- Multiple configurations available
PLDA - Your Trusted Design Partner!
Learn more >> www.plda.com more >>
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