May 15, 2012   
Xilinx Unveils Vivado Design Suite for the Next Decade of 'All-Programmable' Devices
 
Mike Santarini
Xilinx, Inc.
State-of-the-art EDA technologies and methods underlie a new tool suite that will radically improve design productivity and quality of results, allowing designers to create better systems faster and with fewer chips.

After four years of development and a year of beta testing, Xilinx is making its VivadoTM Design Suite available to customers via its early-access program, ahead of public access this summer. Vivado provides a highly integrated design environment with a completely new generation of system- to IC-level tools, all built on the backbone of a shared scalable data model and a common debug environment.
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GLOBALFOUNDRIES - Creating Exceptional Solutions Through True Collaboration. more >>
KW800 14-bit ADC with Programmable Anti-Alias Filter, Clock and Decimation. more >>
Four Channel LVDS Receiver/Deserializer IP - Designed for Chartered 130nm
from Mixel
MIPI D-PHY Source Synchronous Macro for MIPI DSI, CSI and UniPro
from Mixel
10-bit 2MS/s Voltage DAC in 90nm
from S3 Group
OTP/eMTP: 64 Kbit NVM in 65nm Standard Logic CMOS process
from Sidense
OTP/eMTP: 512 Kbit NVM in 90nm Standard Logic CMOS process
from Sidense
I2C Bus Controller Master/Slave
from CAST
HDLC Protocol Controller Core
from CAST
HDMI 1.4 TX PHY 3.4Gbps in TSMC 65nm GP 2.5V from Synopsys
Dual 12-bit 160MSps DAC from
Alvand Technologies
DDR3/2 PHY - TSMC 28HPM18
from Synopsys
MIPI MPHY Receiver supporting up to 3Gbps (HS-G2) data-rate meant...
from Cosmic Circuits
MIPI MPHY Receiver Supporting both HS-G1 and HS-G2 modes
from Cosmic Circuits
Phase-locked loop frequency synthesizer from NTLab
12-bit R/2R DAC from NTLab
HD/2K Math. Lossless JPEG 2000 Decoder from intoPIX
HD/2K Math. Lossless JPEG 2000 Encoder - for Archiving applications
from intoPIX
MACsec (L2 Sec) 10G Processing Engine from Posedge Inc.
MIPI SLIMbus Device Controller
from Evatronix
GSMC 0.18?m 5v-5v/3v/1.8v Power Regulator from VeriSilicon
GSMC 0.18um 3.3V Power on Reset
from VeriSilicon
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PCIe & USB3 IP Cores
 
Leader in MEMS Design Tools
 
GPS+GLONASS+ GALILEO chipset
Low Power Medical Processor
 


 


 


 
AES Encrypt/Decrypt Core
from CAST
Reed Solomon Decoder from Xilinx
32kB EEPROM array with high voltage generator and read write...
from Innovision R&T
Cadence Design IP SuperSpeed USB3.0 PHY from Cadence
High-Speed Programmable Multi-Protocol SERDES Macro for GF 65G
from Analog Bits
SDIO 3.0 Device Controller IP for Bluetooth, LTE and 802.11n...
from Aizyc Technology
L1 GPS/Galileo/GLONASS and FM/VHF/UHF/L/S/DVB -T/H/SH RF...
from NTLab
SD4.0 UHS-II PHY from Silicon Library
800MHz ARM Cortex-A8 processor core with 32K 32K cache (Speed...
from ARM
 
True Circuits General Purpose PLL Hard Macros. The General Purpose PLL is a wide range clock multiplier with deskew capability that is ideal for low power, area sensitive and low cost applications. Click here now! more >>
 
Cadence Encounter Digital Technology Provides Netronome with...
Encounter Technology Delivers 29 % Power Reduction on High-Performance 'Green' Network Flow Processor SoCs ...
X-FAB Joins the Interoperable PDK Libraries Alliance and Announces iPDK...
MOUNTAIN VIEW, Calif., May 14, 2012 - The Interoperable PDK Libraries Alliance announced today that X-FAB Silicon Foundries has joined the IPL Alliance, a...
The Importance of Customizable IP Subsystems to be Discussed by...
SANTA CLARA, CA - May 14, 2012 - Steve Roddy, vice president of Marketing, Tensilica, will participate in a panel discussion titled, "Will IP Subsystems...
DSP IP Market Dominated by CEVA with 90% Market Share
CEVA's market share leadership revealed in report by leading research firm The Linley Group; Report also forecasts greater need for programmable DSPs to...

QML Class V Qualification for Space FPGAs...
Newly Qualified Radiation-tolerant RTAX-S/SL FPGAs Available Now ALISO VIEJO, Calif., May 14, 2012- Microsemi Corporation...
Excellicon Selects Verific Design Automation's...
First-Time DAC Exhibitor Integrated SystemVerilog, VHDL Parsers, RTL Elaborator with Timing Constraint Software ...
TowerJazz Introduces Reference Flow 2.0,...
NEWPORT BEACH, California, May 14, 2012 -TowerJazz, the global specialty foundry leader, today announced the release of the most comprehensive 180nm...
XcitePI Chip IO Interconnect Model Extraction and Assessment Tool...
Breakthrough technology provides accurate models essential for high-speed system simulations CAMPBELL, Calif. -...
Mentor Graphics Helps eoSemi Solve the Challenge of Silicon Oscillator...
CONGLETON, England - eoSemi and Mentor Graphics today announced that the Pyxis Custom Design environment, Eldo simulator and Calibre tools have been...
The SoC IP conference, held in Shanghai and Beijing will be attended by...
Bangalore, INDIA and Campbell, California, 11th May, 2012:-Cosmic Circuits will be attending the Annual SoCIP conference, held in Shanghai and Beijing in May...
Fast Core Processor Models of MIPS Technologies' New Aptiv Generation...
OVP Fast Processor Models Developed Under MIPS-Verified Program OXFORD, England - May 10, 2012 - Imperas is...
EVE Becomes Member of the Silicon Integration Initiative
SAN JOSE, CA - May 10, 2012 - AT 49th DAC BOOTH #1926 - EVE, the leader in hardware/software co-verification, announced today that it has become a member...
NSCore celebrates over 150M units in production. With its low voltage (1.0V) READ operation, 'chargepump-less' programming ability, and small footprint, NSCore's one-time programmable (OTP) IP is the customers' choice for applications such as analog trimming, security keys, and code storage. NSCore is a TSMC IP9000 Qualified and "Ready for IBM Technology" certified OTP provider. more >>
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