This ADC has been designed to reduce time to market, risk and cost in the development of analog front-ends. This dual channel ADC accepts an 40MHz input clock to operate at 40Ms/s per channel. The ADC has a pipeline architecture with differential input in order to maximize dynamic range and noise immunity. Digital correction of the 9 MSB bits ensures good linearity approaching Nyquist.
An analog test input signal port allows the normal input to be bypassed for direct ADC testing.
The design does not require any special analog options using the baseline digital CMOS process which means it is highly portable between foundries.
The integrated clamp circuit allows the signal to be AC coupled to the ADC. Alternatively, this clamp circuit can be powered down separately allowing DC coupling of the input signal.
65nm 6 Metal CMOS (No analog options)
1.2V power supply
1 Vpp differential input range
Dual 80MSPS operation
Dynamic performance: 56dB SINAD at fIN = 7.5MHz, 65dB SFDR at fIN = 7.5MHz
DNL 0.5 LSB
INL 1 LSB
Stand-by and power down modes
Analog test input signal port
Datasheet, Characterization Report
Flat Netlist (cdl), Abstract View (lef)
Layout View (gds2), Timing (lib)
Behavioral Model (Verilog)
Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others
"S3 helped us to enter volume production rapidly by achieving first-time-right silicon resulting in a best-in-class performance product. The high level of integration achieved has made it possible to offer customers a low-cost bill of material solution that perfectly meets our customers' requirements. One of the key benefits of engaging with S3 was their ability to combine their silicon-proven IP and professional services to deliver complete solutions. "
Dirk Wieberneit, VP & General Manager of Product Development Micronas