ANA-ADC-10-20-65-T
ANA-ADC-10-20-65-T
Overview:

The ANA-ADC-10-20-65-T targets a wide range of applications, such as video and graphics digitizing, medical imaging, wireless and wired communication, or general purpose data conversion. Our family of ADCs has a generically scalable architecture based on a time interleaved SAR. The patent pending A2DFraming™ technology moves most of the analog complexity into the digital domain, mitigating analog risks while enabling the SoC designer to select the optimum of power/area/speed performance.

Deliverables

Physical layout (.gds), and Physical LEF abstract (.lef)
SPICE netlist (.cdl), and Liberty timing model (.lib)
Integration guide, and Software drivers
Optional views: Verilog netlist (.v), Synthesis Design Constraints (.sdc), Standard Parasitic Exchange Format (SPEF), Fastscan models (.fslib)

Features

10-bit resolution
Sample rates up to 20 MSPS
Input signal bandwidth of 500 MHz
Available in single-, dual-, or multi-channel configuration
INL: 1 LSB enabled by A2Dframing™
DNL: 0.5 LSB enabled by A2Dframing™
Operating temperature from -40°C to 125°C
Power consumption of 3.6 mW at 20 MSPS
Competitive area
Technology: 65 nm/TSMC, all flavors supported

Details

Category

Portability

Process Node

Type

Maturity

Market Category

Bus Interface

QIP Rating

IP Catalog : Analog & Mixed Signal IP : A2D Converter

ASIC

65nm/TSMC

Hard IP

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Automotive Communications Consumer Electronics Data Processing Industrial and Medical Military/Civil Aerospace Others

N/A

This IP is not yet QIP rated.

Vendor

AnaCatum, is a privately held, venture backed, analog semiconductor licensing company, headquar

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Whitepapers

The Case for Developing Custom Analog

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