10-bit, 40 MSPS ADC in 65nm/Fujitsu

Estimate your chip with this semiconductor IP

AnaCatum

IP Name

ANA-ADC-10-40-65-F

Provider

AnaCatum

Description

10-bit, 40 MSPS ADC in 65nm/Fujitsu

Category

IP Catalog : Analog & Mixed Signal IP : A2D Converter

Portability

ASIC

Process Node

65nm/Fujitsu

Type

Hard IP

Maturity

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Overview

The ANA-ADC-10-40-65-F targets a wide range of applications, such as video and graphics digitizing, medical imaging, wireless and wired communication, or general purpose data conversion. Our family of ADCs has a generically scalable architecture based on a time interleaved SAR. The patent pending A2DFraming™ technology moves most of the analog complexity into the digital domain, mitigating analog risks while enabling the SoC designer to select the optimum of power/area/speed performance.

Features

10-bit resolution

Sample rates up to 40 MSPS

Input signal bandwidth of 500 MHz

Available in single-, dual-, or multi-channel configuration

INL: 1 LSB enabled by A2Dframing™

DNL: 0.5 LSB enabled by A2Dframing™

Operating temperature from -40°C to 125°C

Power consumption of 6.4 mW at 40 MSPS

Competitive area

Technology: 65 nm/Fujitsu, all flavors supported

Deliverables

Verilog model & verilog stub (.v), and Verilog AMS models (.vams)

Physical layout (.gds), and Physical LEF abstract (.lef)

SPICE netlist (.cdl), and Liberty timing model (.lib)

Integration guide, and Software drivers

Optional views: Verilog netlist (.v), Synthesis Design Constraints (.sdc), Standard Parasitic Exchange Format (SPEF), Fastscan models (.fslib)

Market Category

Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others

Datasheet

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Bus Interface

N/A

Size

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QIP Rating

This IP is not yet QIP rated.

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