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100G Physical Coding Sublayer IP

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IP Name
100G PCS
Provider

Open-Silicon
Description

100G Physical Coding Sublayer IP
Category
Portability
ASIC, FPGA
Process Node
all
Type
Soft IP
Maturity
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Overview
The 100G PCS is a 100 Gb/s Physical Coding Sublayer (PCS) to be used in high port density switching ASICs. The 100Gb PCS interfaces to ten 10G SerDes as well as MAC and provides PCS functionality with low gate count thus providing area and power savings. The 100Gb PCS is compliant to 802.3ba clause 82 for 100 Gbps (802.3-2008 clause 49 specifies 10Gb PCS of which 100G is a natural extension) operation. The 100G PCS is architected for both ASIC and FPGA implementation using a standard tool flow.
Features
  • PCS Architecture to support the following speed: 1x10Gbps
  • Interfaces to ten SERDES on line side. SERDES operating at 10.312Gbps for 100Gbps operation
  • Implements the following PCS Configurations. 1x100GBASE-R PCS while operating at 100Gbps
  • Flexible clocking options
  • Provides 320-bit data, 40 bit control (optional 256b/32b or 128b/16b) CGMII like interface to the MAC
  • Implements the PCS Register set(s) for operation and control of the PCS modules
  • Capable of interfacing to SERDES Modules with a 64-bit or 32-bit or 16-bit wide data buses
  • Easily contrallable via simple register interface
  • Integrated test pattern/ PRBS generator and checker
  • Low gate count for area and power savings
Market Category
Communications
Datasheet
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Protocols
Ethernet
Gate Count
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QIP Rating  This IP is not yet QIP rated.
 
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Keywords
Node
28nm      40 nm      55 nm      90 nm      150 nm      250 nm     
32nm      45 nm      65 nm      130 nm      180 nm      350 nm     
Foundry
Common Platform
GLOBALFOUNDRIES
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X-FAB
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Category
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Portability
ASIC FPGA Structured
IP Quality
QIP Rated

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