32-bit OTP anti-fuse memory IP with embedded redundancy mechanism and margin check

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INVIA

IP Name

Anti Fuse

Provider

INVIA

Description

32-bit OTP anti-fuse memory IP with embedded redundancy mechanism and margin check

Categories

IP Catalog : Analog & Mixed Signal IP : Other

IP Catalog : Digital Core IP : Memories : Other

IP Catalog : Digital Core IP : Programmable Logic

Portability

ASIC

Process Node

all

Type

Hard IP

Maturity

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Overview

The anti-fuse IP is a 32-bit One-Time Programmable (OTP) memory. Its redundant architecture prevents from reading errors: each individual bit is made of two anti-fuse elementary cells; the bit is considered set when at least one elementary cell is correctly blown.

The anti-fuse sensing consists in evaluating the impedance of the anti-fuse cell by means of current comparison: when the leakage current is smaller than a reference current, the anti-fuse is seen intact; when the leakage current is bigger than a reference current, the anti-fuse is seen blown. The external blowing voltage is controlled through a high-voltage manager.

A margin check mode emulates the worst case value of the blown anti-fuse impedance. If the anti-fuse is evaluated successfully while in margin check mode, the robustness of the anti-fuse read is guaranteed whatever the operating conditions.

A low-power mode reduces significaly the IP consumption current by latching the data bus. Nevertheless, for secure applications, it is recommended not to use this mode in order to protect the IP against bit-flip attack (in normal mode, the anti-fuses are continuously sensed).

Features

32-bit One-Time Programmable (OTP) anti-fuse memory;

redundant architecture preventing from reading errors;

margin check mode evaluating the anti-fuse state reliability;

high-voltage manager controlling the external blowing voltage;

typical operating consumption current lower than 100 uA;

low-power mode consumption current smaller than 1 uA;

wake-up time shorter than 500 us;

power-supply voltage range: 1.2 V ±10%;

operating junction temperature range: -40°C to 125°C;

silicon area smaller than 0.16 mm² in a 65 nm CMOS process.

Deliverables

GDSII and layer map files;

Library Exchange Format (LEF) file;

VHDL behavioral model and Liberty timing file (.lib);

Circuit Description Language (CDL) netlist;

design specification.

Market Category

Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others

Datasheet

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Size

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QIP Rating

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