The anti-fuse IP is a 32-bit One-Time Programmable (OTP) memory. Its redundant architecture prevents from reading errors: each individual bit is made of two anti-fuse elementary cells; the bit is considered set when at least one elementary cell is correctly blown.
The anti-fuse sensing consists in evaluating the impedance of the anti-fuse cell by means of current comparison: when the leakage current is smaller than a reference current, the anti-fuse is seen intact; when the leakage current is bigger than a reference current, the anti-fuse is seen blown. The external blowing voltage is controlled through a high-voltage manager.
A margin check mode emulates the worst case value of the blown anti-fuse impedance. If the anti-fuse is evaluated successfully while in margin check mode, the robustness of the anti-fuse read is guaranteed whatever the operating conditions.
A low-power mode reduces significaly the IP consumption current by latching the data bus. Nevertheless, for secure applications, it is recommended not to use this mode in order to protect the IP against bit-flip attack (in normal mode, the anti-fuses are continuously sensed).