The META HTP 32-bit processor core is a latency-tolerant application processor with a rich DSP feature set, based on a multi-threaded architecture. It enables developers to replace multiple processors and DSP cores with a single unified core. A four-threaded META HTP delivers up to 1610 DMIPS in a 65nm process.
Multi-threaded processor core
Rich DSP feature set
Configurable thread capabilities
I/D caches & memory management unit (MMU)
Optional floating point unit (FPU)
16-bit instruction set support
Fine-grain power management
Non-invasive debugging via JTAG
AMA (Automatic MIPS Allocation) for system load balancing
OS Support: Linux, MeOS, Native (per thread)
Toolchain: gcc, mecc optimising DSP, ODESCAPE IDE
Comprehensive Developer SDK
Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others
"The increasing quantity and sophistication of mobile device applications puts challenging burdens on the industry to enable the superior graphics capabilities with the necessary low power consumption. TI successfully meets those expectations with the integration of Imagination's POWERVR cores. "
Remi El-Ouazzane, Vice President and General Manager, OMAP Platform TI