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40G Physical Coding Sublayer IP

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IP Name
40G PCS
Provider

Open-Silicon
Description

40G Physical Coding Sublayer IP
Category
Portability
ASIC, FPGA
Process Node
all
Type
Soft IP
Maturity
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Overview
The 40Gb PCS is a 40Gb/s Physical Coding Sublayer (PCS) to be used in high port density switching ASICs. The 40Gb PCS interfaces to four 10G SERDES as well as a MAC and provides PCS functionality with low gate count thus providing both area and power savings. The 40Gb PCS is compliant with 802.3ba clause 82 for 40Gbps (802.3-2008 clause 49 specifies 10Gb PCS of which 40G is a natural extension) operation. The 40G PCS is architected for both ASIC and FPGA implementations.
Features
  • PCS Architecture to support the following speed: 1x40Gbps
  • Interfaces to four SERDES on line side. SERDES operating at 10.312Gbps for 40Gbps operation
  • Implements the following PCS Configurations. 1x40GBASE-R PCS while operating at 40Gbps
  • Provides 128-bit data, 16 bit control XLGMII like interface the MAC. Alternatively provides 64-bit data, 8 bit control XLGMII interface for narrower data path
  • Implements the PCS Register set(s) for operation and control of the PCS modules
  • Capable of interfacing to SERDES Modules with a 64-bit or 32-bit or 16-bit wide data buses
Market Category
Communications
Datasheet
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Protocols
Ethernet
Gate Count
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QIP Rating  This IP is not yet QIP rated.
 
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