C65C02
C65C02
Overview:

The C6502 is a fast 8-bit microprocessor IP core that implements the same instruction set as the 65C02 microprocessor, which is an upgraded version
of the popular NMOS-based MOS Technology 6502 8-bit CPU. The C65C02 provides software and hardware interrupts for interfacing external devices.
With sixteen addressing modes, including indirect index and zero page, the C6502 is able to address up to 64KB of external memory with two byte long
instructions. The 8-bit arithmetic-logic unit can operate on signed and unsigned binary numbers as well as binary-coded decimal numbers. The C65C02 core offers two instructions for efficient power management: STP for halt processor and WAI for wait for interrupt instruction.

Deliverables

Synthesis support for Synopsys® tools with a set of synthesis scripts
Simulation support for Mentor Graphics® and Cadence® tools with a set of scripts and macros
Extensive VHDL/Verilog 2001 test bench, Documentation, a collection of 65C02 assembler programs
30 days of technical support, 90 days of warranty against defects

Features

65C02 ISA compliant
Control Unit with both maskable and non-maskable interrupts
8-bit Instruction Decoder with 69 instructions and 212 documented opcodes
8-bit ALU for decimal and binary arithmetic as well as logical/ logical shift operations
External Memory interface addressing up to 64KB of memory through 16 addressing modes
Power saving mode

Details

Category

Portability

Process Node

Type

Maturity

Market Category

QIP Rating

IP Catalog : Digital Core IP : Microcontrollers : CISC

ASIC, FPGA, Structured

all

Soft IP

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Automotive Communications Consumer Electronics Data Processing Industrial and Medical Military/Civil Aerospace Others

This IP is not yet QIP rated.

Vendor

Evatronix develops digital and mixed-signal Intellectual Property (IP) cores with complementary

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