80251 CPU core
80251 CPU core
Overview:

The 80251 CPU IP core is an instruction set compatible implementation of the MCS-251 family. The 80251 core executes the instruction in a single clock cycle, and is on average about 3.19 times faster than the original implementation. The performance improvements are due to architectural enhancements done to the CPU core. The I/O ports of the IP core have been simplified by removing unnecessary muxing on the ports to make it fully compatible with today's system on chip (SoC) design practices.

Features

Single clock cycle instruction execution
Up to 16Kbytes of on-chip program memory
1024 bytes of on-chip data RAM
Up to 64Kbytes of external program memory
Up to 16M bytes of external data memory reserve for ROM/RAM
Enhanced architecture for performance improvements
Wait state support for slow external peripherals
Standard 2 16-bit timers/counters
6 source/5 vector interrupt structure with two priority levels
Optional components are available as part of 80251 platform

Details

Category

Portability

Process Node

Type

Maturity

Market Category

QIP Rating

IP Catalog : Digital Core IP : Microcontrollers : Other

ASIC, FPGA

all

Soft IP

Please login or register to view this data

Automotive Communications Consumer Electronics Data Processing

This IP is not yet QIP rated.

Vendor

Open-Silicon, Inc., a leading semiconductor design and manufacturing company and founding membe

CONTACT VENDOR

Find the component you need without hours of searching.

Testimonials

No testimonials yet

Whitepapers

The Case for Developing Custom Analog

The contents of this document are owned or controlled by S3 Group and are protected under applicab...

DOWNLOAD