The IPX-AES-MD Decryptor IP-Core provides an efficient FPGA implementation of the Advanced Encryption Standard (AES). Its flexibility allows the combination of several functions and operating modes for a very small FPGA footprint.
The IPX-AES-MD IP-Core is a 1Gbps Multi Assets Decryptor core that efficiently implements in FPGA the Advanced Encryption Standard as specified in the Federal Information Processing publication FIPS-197 of the National Institute of Standards and Technology.
The IPX-AES-MD can be customized to ensure its optimization for a wide range of specific application fields with a design architecture that can be adapted to support from low up to very high bit-rates. Its flexibility allows combining several functions and operating modes on very small footprints.
AES Decryption : 1Gbps Multi Assets Decryptor
Throughput bit rate: 2,5Gbps
Data-stream handling : Single or Multiple streams (up to 16)
Operation modes: ECB, CBC
AES Data and Key Bus widths : 128 bits
Ultra Low footprint
RTL code or Netlist (depending on license type)
Functional simulation testbench
Data Processing, Industrial and Medical, Military/Civil Aerospace, Others