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JetAES - Standard Core

JetAES - Standard Core

Overview:

The JetAES Standard encryption and decryption IP cores implement the AES (Rijndael) encryption standard, as described in the NIST Federal Information Processing Standard (FIPS) Publication 197. The cores are designed to be highly flexible and can be integrated into any AES design with ease. Different options are available for achieving the best speed/area results for specific applications. The cores support both encryption and decryption functionality and can be used with all or any of the three AES key sizes (128, 192, 256-bit). The cores are available for licensing in both source and netlist form.

Deliverables

For HDL Licenses : Fully synthesizable RTL Verilog source

Self-checking test bench

Simulation script, test vectors and expected results

User documentation

Features

Fully compliant with AES described in NIST FIPS 197

Medium speed: throughput over 700 Mbps

Simple interface & fully synchronous design

Flow-through design

32-bit wide data path processes each round in 4 clock cycles

User programmable key size of 128, 192 or 256-bit change dynamically with on-the-fly hardware key expansion and no dead cycle when changing keys

Separate and Combined cores for encryption and decryption are available

Supports ECB mode. Optional wrapper is included to support all AES classic block cipher modes like CBC, CFB, OFB or CTR

Available solutions for more advanced "modes" of AES, such as AES-CCM, AES-GCM, LRW-AES

Self-checking test bench with FIPS test vectors

Details

Category

Portability

Process Node

Type

Maturity

Market Category

QIP Rating

IP Catalog : Digital Core IP : Security : Decryption
IP Catalog : Digital Core IP : Security : Encryption

ASIC, FPGA, Structured

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Soft IP

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Communications Data Processing Industrial and Medical Military/Civil Aerospace

This IP is not yet QIP rated.

Vendor

Jetstream Media Technologies offers a broad product line of security IP cores for SoC and FPGA

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Whitepapers

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