The AES-GCM10G core is an enhanced and optimised version of Algotronix standard AES-GCM design targetted at 10Gbit IEEE 802.1 networking. The core delivers 10Gbit/sec throughput under worst case conditions (minimum sized packets and key changes for each packet). This level of performance is achieved with a 156MHz clock bringing the application within the reach of modern FPGAs. The core is supplied as source code and can also be licensed for use on ASIC.
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