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AES-GCM10G

AES-GCM10G

Overview:

The AES-GCM10G core is an enhanced and optimised version of Algotronix standard AES-GCM design targetted at 10Gbit IEEE 802.1 networking. The core delivers 10Gbit/sec throughput under worst case conditions (minimum sized packets and key changes for each packet). This level of performance is achieved with a 156MHz clock bringing the application within the reach of modern FPGAs. The core is supplied as source code and can also be licensed for use on ASIC.

Deliverables

Comprehensive self-checking testbench

Features

10Gbit/sec performance under worst case conditions

156MHz clock frequency allows timing closure on FPGA

Overlapped processing maintains throughput on minium size packets

Pass through mode for non-MACSEC packets

Supplied as source code to allow security review

Targets Xilinx and Altera FPGA families

Based on proven AES-G3 Advanced Encryption Standard core

Area efficient implementation

Details

Category

Portability

Process Node

Type

Maturity

Market Category

QIP Rating

IP Catalog : Digital Core IP : Communications : Other
IP Catalog : Digital Core IP : Security : Decryption
IP Catalog : Digital Core IP : Security : Encryption

FPGA

Soft IP

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Communications

This IP is not yet QIP rated.

Vendor

Algotronix specialises in the implementation of the Advanced Encryption Algorithm (AES) and rel

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