ATA-7 compliant host controller core used for interfacing ATA devices like hard-disks and CD/DVD drives. Core is targeted for SOC implementations in ASIC and FPGA.
Features
PIO modes 0-4
Multi-word DMA modes 0-2
Ultra DMA modes 0-6
Programmable timings for PIO and DMA modes
Support for Ultra DMA pause and termination
Standard slave Wishbone interface to microprocessor/microcontroller
Interrupt generator for IRQ driven software driver implementation
Transparent (pass through) access from processor interface to device task registers
DMA engine and master Wishbone interface for data transfer
Small register FIFOs for transmit and receive data
Deliverables
Verilog source code or netlist
Test Bench (Verilog Source Code)
Documentation
Reference design incl. C code
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Market Category
Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others