ATA7_TARGET1

Overview:

This is a ATA-7 compliant device interface core used for interfacing custom devices to IDE controller. Core is targeted for SOC implementations in ASIC and FPGA.

Deliverables

Test Bench (Verilog Source Code)

Documentation

Reference design incl. C code

Free Tech Support

Features

PIO modes 0-4

IORDY signaling for PIO cycle extension

Multi-word DMA modes 0-2

Ultra DMA modes 0-6

Programmable timings for PIO and DMA modes

Support for Ultra DMA pause and termination

Automatic handling of BSY and DRQ bits

Build in DMA engine and master interface

WISHBONE, AHB, OPB, PLB, OCP and AVALON SoC Interface

66MHz clock for UDMA133 (mode 6) operation

Details

Category

Portability

Process Node

Type

Maturity

Market Category

Bus Interface

QIP Rating

IP Catalog : Digital Core IP : Controllers : Disk
IP Catalog : Digital Core IP : Controllers : Storage

ASIC, FPGA, Structured

45nm

Soft IP

Please login or register to view this data

Automotive Communications Consumer Electronics Data Processing Industrial and Medical Military/Civil Aerospace Others

WISHBONE, AHB, OPB, PLB, OCP and AVALON

This IP is not yet QIP rated.

Vendor

ASICs World Services specialize in providing top-notch IP Cores and design services. We will as

CONTACT VENDOR

Find the component you need without hours of searching.

View Vendor Profile ›

Testimonials

No testimonials yet

View All ›

Whitepapers

The Case for Developing Custom Analog

The contents of this document are owned or controlled by S3 Group and are protected under applicab...

DOWNLOAD