The AXI Interconnect IP connects one or more AXI memory-mapped Master devices to one or more memory-mapped Slave devices. The AXI interfaces conform to the AMBA® AXI version 4 specifications from ARM®, including the AXI4-Lite control register interface subset. The Interconnect IP is intended for memory-mapped transfers only; AXI4-Stream transfers are not applicable. The AXI Interconnect IP can be used as a pcore from the Embedded Development ToolKit (EDK) or as a standalone core from the CORE Generator IP catalog.
Key Features in EDK
Selectable interconnect architecture
Crossbar mode (Performance optimized): Shared-Address, Multiple-Data (SAMD) crossbar architecture with parallel pathways for write and read data channels
Shared Access mode (Area optimized): Shared write data, shared read data, and single shared address pathways.
AXI protocol compliant (AXI3, AXI4, and AXI4-Lite) includes:
Burst lengths up to 256 for incremental (INCR) bursts
Converts AXI4 bursts > 16 beats when targeting AXI3 slave devices by splitting transactions
Generates REGION outputs for use by slave devices with multiple address decode ranges
Propagates USER signals on each channel, if any; independent USER signal width per channel (optional)
Propagates Quality of Service (QoS) signals, if any; not used by the AXI Interconnect core (optional)
Interface data widths:
AXI4: 32, 64, 128, 256, 512, or 1024 bits
AXI4-Lite: 32 bits
32-bit address width
Connects to 1-16 master devices and to 1-16 slave devices