AltraCores GZIP IP Core - Exceptional Performance, Small Footprint, Multiple Configurations, Optimal Compression and Throughput

Estimate your chip with this semiconductor IP

Altior

IP Name

GZIP 2104

Provider

Altior

Description

AltraCores GZIP IP Core - Exceptional Performance, Small Footprint, Multiple Configurations, Optimal Compression and Throughput

Category

IP Catalog : Digital Core IP : Communications : Other

Portability

ASIC, FPGA, Structured

Process Node

65nm

Type

Soft IP

Maturity

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Overview

The AltraCores™ GZIP Core is a flexible, easy to integrate IP core that performs standards based,
lossless compression. The compression core can operate in tandem with the AltraCores GUNZIP Core (decompression), or independently with industry-standard software.

The AltraCores GZIP Core provides exceptional performance, small footprint, and offers
multiple configurations to ensure optimal compression and throughput.

Ideal for both storage and networking devices, the AltraCores GZIP Core is designed to meet
the needs of high-performance environments. The AltraCores GZIP Core enables designers to efficiently utilize valuable storage space without sacrificing performance while reducing
overall BOM (Bill of Materials) costs. The AltraCores GZIP Core efficiently compresses
data by offloading the computational-intensive compression tasks from the CPU without data loss. The AltraCores GZIP Core enables networking solutions designers to increase bandwidth usage, and significantly reduce their operating costs.

Features

Patent-free algorithm

High performance

Compression ratios up to 3:1

Easily aggregated for very high throughputs (533 Mbps to 9.4 Gbps)

Industry standard algorithms: ZLIB and GZIP

Highly configurable to balance throughput, compression, and chip resource requirements

Fully synchronous design

Customizable history window sizes (4 KB, 8 KB, 16 KB, 32 KB)

Configurable hash table length to optimize memory area

Easily integrated with AltraFlex aggregation wrappers

Deliverables

Synthesizable Verilog RTL

Verilog test bench and test suite

ASIC and FPGA synthesis scripts

ASIC DFT and layout guidelines

Optional C Models

Market Category

Communications

Datasheet

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Gate Count

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QIP Rating

This IP is not yet QIP rated.

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