Based on GSMC 0.13?m IBLP 4P5M Dual Gate e-flash process (1.5v/HV), current design of the IP detects light with photodiode. When

Estimate your chip with this semiconductor IP

VeriSilicon

IP Name

G13LPDG_LDWPD_01

Provider

VeriSilicon

Description

Based on GSMC 0.13?m IBLP 4P5M Dual Gate e-flash process (1.5v/HV), current design of the IP detects light with photodiode. When

Category

IP Catalog : Analog & Mixed Signal IP : Other

Portability

ASIC

Process Node

130nm/Grace

Type

Hard IP

Maturity

Please login or register to view this data

Overview

Based on GSMC 0.13?m 1.5V/12V eFlash process, current design of the IP detects light with photodiode. When the incident light power is more than 70mW/m2, the output is low; otherwise, the output is high.

Features

Process: GSMC 0.13um IBLP 4P5M dual gate e-flash process (1.5v/HV)

MOS devices being used: nch, pch

Wavelength range of spectral response: 400nm~1100nm

Peak sensitivity wavelength: 900nm

Current responsibility: 0.2A/W@600nm

Dark current: <10pA

Settling time: 20us

Typical current consumption: 100uA

Power down current: 0.1uA

More details, please go to below website to contact VeriSilicon location sales : http://www.verisilicon.com/en/contactus.asp

Market Category

Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others

Datasheet

Please login or register to view this data

Size

Please login or register to view this data

QIP Rating

This IP is not yet QIP rated.

Related IP from VeriSilicon you may be interested in...

	IP Name			Description
	SMIC18_CLOCKSLICER_01			SMIC 0.18um Clock Slicer
	SMIC18_CP_01			3V-5V Charge Pump for USB OTG
	S13V25_CCP2RX _01			Sub-LVDS receiver followed by 1:4 de-serializer
	SMIC18_PWM_01			SMIC 0.18um PWM Boost DC/DC Controller
	S13V25_CCP2TX_01			32:1 serializer followed by sub-LVDS drivers