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C13V25_PLL_01

C13V25_PLL_01

Overview:

This IP is a programmable Analog PLL suitable for high speed clock generation. High speed VCO can run from 50MHz to 500MHz. By setting different values of DM(5:0) and DN(6:0) according to different REFIN, CLK will be locked at the multiples of input frequency.

Features

Process: Charter 0.13um Dual-Gate (1.2V/2.5V) Nominal with Multi-Vt Process

Supply voltage: 1.0v~1.2v~1.32v

Current: <2.5mA

Operating junction temperature: - 40Â°C ~ +25Â°C ~ +125Â°C

More details, please go to below website to contact VeriSilicon location sales : http://www.verisilicon.com/en/contactus.asp

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IP Catalog : Analog & Mixed Signal IP : Clock : PLL

ASIC

130nm/GLOBALFOUNDRIES

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Founded in 2001, VeriSilicon Holdings Co., Ltd. ("VeriSilicon") is a fast growing silicon solut

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