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DDR3 Memory Controller IP

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Uniquify
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IP Name
DDRC 1600A
Provider

Uniquify
Description

DDR3 Memory Controller IP
Category
Portability
ASIC, FPGA
Process Node
all
Type
Soft IP
Maturity
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Overview
Uniquify offers a high performance, flexible, user-friendly memory controller design that greatly reduces customer effort needed to meet DDR interface timing requirements.
Features
  • Automatic Self-Configuring Logic (SCL) technology eliminates system level timing issues
  • Low read data capture latency
  • Fast turn-around time between read and write operations
  • Optimum design closure through DFI PHY macros
  • Chip/system yield improvement through SCL (DFY)
  • Embedded chip/system testability (DFT)
  • Parameterizable data bus and ECC width
  • Deep command pipeline support
  • Support for built in read-modify-write
  • Fully configurable ODT window
Deliverables
  • Memory controller IP
  • Digital DLL
  • DFI PHY physical interface
  • Read write logic implemented as medium or hard macro
  • Fully self-checking, randomized test environment
Market Category
Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others
Datasheet
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Bus Interface
AMBA AHB, AMBA AXI
Gate Count
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QIP Rating  This IP is not yet QIP rated.
 
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Keywords
Node
28nm      40 nm      55 nm      90 nm      150 nm      250 nm     
32nm      45 nm      65 nm      130 nm      180 nm      350 nm     
Foundry
Common Platform
GLOBALFOUNDRIES
IBM
 SilTerra
SMIC
TSMC
 Tower
UMC
X-FAB
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Category
Vendor
Portability
ASIC FPGA Structured
IP Quality
QIP Rated

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