ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog ChipEstimate.com Chip Planning Portal and Semiconductor IP Catalog
Visit IP Talks at DAC 2013 to learn the latest about semiconductor IP
Advertise on the world's largest semiconductor IP catalog at ChipEstimate.com Advertise on the world's largest semiconductor IP catalog at ChipEstimate.com
Advertise on the world's largest semiconductor IP catalog at ChipEstimate.com
Home  :  Search IP  :  IP Details

DLL - GF/CP L65LPE 65nm DDR DLL - 78MHz-390MHz

 Estimate your chip with this semiconductor IP
True Circuits
Semiconductor IP Vendor InformationView all semiconductor IP from True CircuitsContact Semiconductor IP VendorSemiconductor IP Customer Testimonials Add Semiconductor IP to an IP List

Share
Email Semiconductor IP Datasheet Print Semiconductor IP Datasheet   
IP Name
TCI-CL65LPE-DDRLDLL
Provider

True Circuits
Description

DLL - GF/CP L65LPE 65nm DDR DLL - 78MHz-390MHz
Categories
Portability
ASIC, FPGA, Structured
Process Node
65nm/Common Platform/L65LPE    
Type
Hard IP
Maturity
Please login or register to view this data
Overview
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay line which rejects temperature and supply voltage variations, and has high supply noise rejection for very low jitter operation. TCI can configure this block to have almost any number of slaves (which delay the arbitrary signals) with a single master section (which establishes the time base) to minimize area and power. The slave delays can be independently set to precise values or dynamically adjusted after determining the boundaries of a data eye. The DDR DLL has excellent linearity and very high resolution. TCI can also configure this block to output multi-phase clocks directly from the reference clock.
Features
  • - Designed for high-speed DDR style interface applications.
  • - Generates precise delays that can be programmed from 0 to 360 degrees of the reference period.
  • - delays multiple periodic or aperiodic signals independent of voltage and temperature.
  • - Optionally outputs multi-phase clocks directly from the reference clock.
  • - Delivers optimal jitter performance over a wide frequency range.
  • - Available in flexible form factors for easier integration.
Deliverables
  • - GDSII (100% DRC and LVS clean)
  • - LVS Spice netlist
  • - Verilog model
  • - Synopsys synthesis model
  • - LEF for clock generator PLL
Market Category
Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others
Datasheet
Please login or register to view this data
Protocols
Bluetooth
DDR2
DDR3
DDR4
DigRF
DSL
Ethernet
FibreChannel
HDMI
HyperTransport
Infiniband
PCI
RapidIO
SATA1.0
SATA2.0
SATA3.0
SCSI
SPI-4.1
SPI-4.2
USB1.1
USB2.0
WiMax
Size
Please login or register to view this data
QIP Rating  This IP is not yet QIP rated.
Customer Testimonial

"Our mission is to provide predictable, reliable and cost-effective ASIC solutions, while reducing risk at each step of the process and improving time-to-market. True Circuits PLLs and DLLs are feature rich, easily integrated and well supported, helping us to deliver quality analog IP and faster design implementations to our ASIC customers. "

Hans Bouwmeester, Director of IP
Open-Silicon, Inc.
 
 
     Related IP from True Circuits you may be interested in...
IP Name Description
TCI-U13SP-SSMPLL PLL - UMC L130SP 130nm Spread Spectrum PLL - 118MHz-590MHz
TCI-U13SP-SSLPLL PLL - UMC L130SP 130nm Spread Spectrum PLL - 59MHz-295MHz
TCI-U13SP-SSHPLL PLL - UMC L130SP 130nm Spread Spectrum PLL - 236MHz-1180MHz
TCI-U13SP-LBMPLL PLL - UMC L130SP 130nm Low bandwidth PLL - 118MHz-590MHz
TCI-U13SP-LBLPLL PLL - UMC L130SP 130nm Low bandwidth PLL - 59MHz-295MHz
 
 
Search For Semiconductor Design and Verification IP
Keywords
Node
28nm      40 nm      55 nm      90 nm      150 nm      250 nm     
32nm      45 nm      65 nm      130 nm      180 nm      350 nm     
Foundry
Common Platform
GLOBALFOUNDRIES
IBM
 SilTerra
SMIC
TSMC
 Tower
UMC
X-FAB
advertisement
Category
Vendor
Portability
ASIC FPGA Structured
IP Quality
QIP Rated

     Language: Search for Semiconductor Design and Verification IP at ChipEstimate.com English | Search for Semiconductor Design and Verification IP at ChipEstimate.jp Japanese | Search for Semiconductor Design and Verification IP at ChipEstimate.cn Chinese
 
      ChipEstimate.com Chip Planning & IP Portal -- Copyright © 2013 ChipEstimate.com. All rights reserved.
ChipEstimate.com Twitter feed  ChipEstimate.com Semiconductor IP on LinkedIn  ChipEstimate.com Semiconductor IP Channel on YouTube  ChipEstimate.com Semiconductor IP on Facebook  ChipEstimate.com Semiconductor IP on Google+ 


       Feedback  Privacy Policy  Terms of Use  Newsletter & Tech Talk Archive  IP Catalog Site Map