Denali's Databahn Synthesizable DDR DRAM PHY is a third-generation, DFI-compliant PHY IP block which is a complete process-independent solution ready to be integrated into SoCs and ASICs which interface with DDR DRAM memories. Each configurable PHY is delivered to match the unique requirements of the customer's DDR application. Using Denali's PHY reduces risk and time-to-market for deploying memory interfaces in silicon.
Achieve a GHz PHY (DDR-2133 data rates), including synthesis, layout, and timing closure in four hours using a standard EDA toolset
Process node independent
Configurable for data width, ECC, low power, and many other options
"At Freescale, we needed a solution that would enable us to meet our SoC design requirements in a fast and efficient way while preserving quality. Denali's DDR memory controller IP enables our designers to rapidly address customer design requirements and applications. Denali's memory controller IP used in our chips, helps us to meet our customers' needs for low power consumption for mobile phones. "
Raja Tabet, Director of Solutions and Enablement Technology Freescale Semiconductor