Databahn DDR3/2/1DDR SDRAM PHY in TSMC 65LP

Estimate your chip with this semiconductor IP

Denali Software

IP Name

DDR3/DDR-SDRAM PHY-TSMC 65LP

Provider

Denali Software

Description

Databahn DDR3/2/1DDR SDRAM PHY in TSMC 65LP

Categories

IP Catalog : Off-Chip Interface IP : Bus Interface IP : SSTL

IP Catalog : Off-Chip Interface IP : Embedded I/O Cores : PHY

Portability

ASIC

Process Node

65nm

Type

Soft IP

Maturity

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Overview

Denali's Databahn Synthesizable DDR DRAM PHY is a third-generation, DFI-compliant PHY IP block which is a complete process-independent solution ready to be integrated into SoCs and ASICs which interface with DDR DRAM memories. Each configurable PHY is delivered to match the unique requirements of the customer's DDR application. Using Denali's PHY reduces risk and time-to-market for deploying memory interfaces in silicon.

Features

Achieve a GHz PHY (DDR-2133 data rates), including synthesis, layout, and timing closure in four hours using a standard EDA toolset

Process node independent

Configurable for data width, ECC, low power, and many other options

Supports DDR3/2/1 and LP-DDR1/2 devices

Market Category

Communications, Consumer Electronics, Others

Datasheet

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Gate Count

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QIP Rating

This IP is QIP rated.

Customer Testimonial

"At Freescale, we needed a solution that would enable us to meet our SoC design requirements in a fast and efficient way while preserving quality. Denali's DDR memory controller IP enables our designers to rapidly address customer design requirements and applications. Denali's memory controller IP used in our chips, helps us to meet our customers' needs for low power consumption for mobile phones. "

Raja Tabet, Director of Solutions and Enablement Technology
Freescale Semiconductor

View More Testimonials

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