The Diamond 212GP CPU is a high performance, versatile, fully synthesizable 32-bit RISC SOC controller core. Not only is the Diamond 212GP efficient area-wise and power-wise, its local memory architecture provides outstanding flexibility and performance. Users can take advantage of Tensilica's lockable cache and attach any size single-cycle instruction or data SRAM up to 128Kbytes. Since Diamond 212GP target applications are controller related, interrupt options are extremely important. The cores include a non-maskable interrupt for critical system events, and five levels of interrupts consisting of a combination of external, software, and timer interrupts. This eases the development of software interrupt handlers and external interrupt priority hardware design. In addition, DSP hardware support on chip reduces the need to include a separate DSP in the system design. DSP support in the Diamond 212GP consists of a single-cycle 16bitX16bit MAC unit adding four dedicated 32-bit registers and a 40-bit accumulator. Additionally, there is support for zero-overhead looping, clamps (saturating arithmetic), max/min value, normalize, and sign extend.
Flexible memory architecture adaptable to an extremely wide range of applications
8K, 2-way Instruction and Data caches
0-128 Kbyte tightly coupled local instruction RAM and data RAM
15 interrupts with 6 priority levels
Single-cycle 16X16-bit MAC
DSP instructions eliminate need for separate DSP: 16x16 MAC/MUL, Min/Max, Clamps, Sign Extend, NSA
1.3 DMIPS/MHz performance
32-bit input and 32-bit output GPIO pins
On-chip debug decreases time to market
Drops into existing AMBA-based systems
Compiler, ISS, debugger, etc.
Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others
"We are delighted to be working with Tensilica and integrating their unique and high-quality digital signal processing IP cores into our solutions to enhance the quality of the consumer audio experience. "