Full chip, configurable ESD protection design kit with GDSII, documentation, tools and support

Estimate your chip with this semiconductor IP

SOFICS - Solutions for ICs

IP Name

UMC 90nm ESD cells

Provider

SOFICS - Solutions for ICs

Description

Full chip, configurable ESD protection design kit with GDSII, documentation, tools and support

Categories

IP Catalog : Off-Chip Interface IP : Embedded I/O Cores : Serdes

IP Catalog : Off-Chip Interface IP : I/O Libraries : General Purpose I/O

IP Catalog : Off-Chip Interface IP : I/O Libraries : Specialty I/O

Portability

ASIC, FPGA, Structured

Process Node

90nm/UMC

Type

Hard IP

Maturity

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Overview

TakeCharge Design Kits (TDK) are available for all advanced CMOS nodes: 180nm down to 65nm. The ESD protection library elements (GDSII) provide a complete solution set, covering all ESD aspects of single IO up to full System-on-Chip design (SoC). The TakeCharge Design Kit tools guide the designers to ESD protection for standard as well as specialty I/O structures.

Features

scaleable ESD protection cells - any ESD specification

Standard specifications 2kV HBM - 200V MM

Enable high speed interfaces 1-12 Gbps without signal distortions

Low capacitive solutions: <100fF for 2kV HBM

Silicon and product proven in >600 high volume IC's

Fully configurable ESD solutions

Patent protection

Reduced design time

on-chip Electrostatic Discharge Protection

SOFICS, formerly Sarnoff Europe

Deliverables

GDSII database with reference ESD solutions for all IO types

Simulation tool to verify and optimize full IC protection levels

Decision tree - easily select the correct ESD protection approach and clamp

Documentation

2 day training and implementation support (layout review)

Market Category

Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace, Others

Datasheet

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Size

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QIP Rating

This IP is not yet QIP rated.

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