High Density Contact/Via 23 ROM 1M Sync Compiler, TSMC 130LVOD SVt

Estimate your chip with this semiconductor IP

Synopsys

IP Name

Embedded Memory, 1- Port, Contact/Via 23 ROM, Compiler, TSMC 130LVOD SVt

Provider

Synopsys

Description

High Density Contact/Via 23 ROM 1M Sync Compiler, TSMC 130LVOD SVt

Category

IP Catalog : Digital Core IP : Memories : ROM

Portability

ASIC

Process Node

130nm/TSMC/LV-OD

Type

Hard IP

Maturity

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Overview

Synopsys' DesignWare® ASAP™ Memory product line represents the largest selection of silicon-proven, low risk, easy to integrate, embedded memory IP available today. Hundreds of memory compilers are available ranging from 250-nm to 65-nm and spanning many foundries to address the demanding requirements of density, speed and power. Synopsys has architected three separate families of sub-megabit embedded memory compilers under the Area, Speed, and Power (ASAP) Memory product line. The High-Density (HD) memories address the needs of many applications that are optimized for area; the High-Speed (HS) memories address the requirements of high-performance systems; and the Ultra-Low Power (ULP) memories address the needs of power-sensitive portable applications. The Ultra-Low-Power architecture involves using techniques such as self-timed clocking, clock-partitioning, reduced bit-line swing, and array banking to deliver the lowest possible power. Sophisticated power models based on SPICE provide detailed and accurate power models for system integration. End-of-cycle shut-off logic and the addition of a memory disable pin ensure zero quiescent current regardless of the state of the clock or input pins, thereby facilitating very low power consumption when the memory is idle. The advanced Ultra-Low-Power architecture has been in used for designs as long ago as 180-nm. The High-Density (HD) address the area sensitive needs required in today's competitive system-on-chip (SoC) design environment while leveraging design techniques to optimize area without compromising on quality and ensure accurate test chip validation. The High-Speed memory architecture leverages state-of-the-art circuit techniques and rigid design practices to ensure high-performance does not come as the price of quality. The advanced design techniques used ensure tight internal timing controls across all process corners, operating voltages and temperatures. Some of these advanced design techniques include high-speed sense amplifiers, fast clocking, and fast bit-line recovery, which contribute to achieving the high-speeds required by today's high-performance applications. Synopsys' DesignWare STAR Memory System includes self-testable and repairable memories ranging in size from the smallest register files (RF) to the largest multi-megabit memories, or integrate with most third-party BIST engines.

Features

The High-Density family consists of: 1 Port Register File, 2 Port Register File, Single Port SRAM, Dual Port SRAM, ROM

The ROM Compiler generates instances that may be programmed by a ROM programming tool

Synopsys' High-Speed (HS) memories are architected to meet high-performance requirements without compromising product quality

The High-Speed family consists of: Single Port SRAM, Dual Port SRAM, 1 Port Register File, Multiport Register File

Ultra-Low-Power (ULP) memory architecture enable users to take advantage of memories with reduced active and leakage power required to support the needs of today's portable and battery operated products

All DesignWare ASAP Memories can optionally include the comprehensive Built-In-Self-Test (BIST) implementation found in Synopsys' DesignWare STAR Memory System

DesignWare STAR Memory provides embedded memories designed for testability and manufacturing to optimize yield

Building on the DesignWare ASAP Memory product line, DesignWare STAR Memories include redundancy capabilities for repair purposes

Deliverables

.lib

LEF

GDS

Verilog

CDL and other industry standard design views

Market Category

Communications, Consumer Electronics, Data Processing, Military/Civil Aerospace, Others

Datasheet

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Size

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QIP Rating

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Customer Testimonial

"Developing the [USB] IP internally was never an option for us because it is not our core competency. Compared to other IP vendors we evaluated, Synopsys DesignWare USB 2.0 nanoPHY was 30% lower in area and up to 15% lower in power. It was one of the smallest PHYs we found. "

Laurent Sibony, Director of ASIC Designs
Sequans

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