High Performance AES Crypto Engine

Estimate your chip with this semiconductor IP

Posedge Inc.

IP Name

Posedge AES Crypto Engine

Provider

Posedge Inc.

Description

High Performance AES Crypto Engine

Categories

IP Catalog : Digital Core IP : Security : Authentication

IP Catalog : Digital Core IP : Security : Decryption

IP Catalog : Digital Core IP : Security : Encryption

Portability

ASIC, FPGA

Process Node

all

Type

Soft IP

Maturity

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Overview

AES Crypto Engine IP is a Silicon-proven high performance crypto core. The core is flexible and can be configured for various data rates and sizes depending on the application. The design supports EBC, CBC, and CTR modes of operation and is used in variety of applications including high end security devices implementing IPSEC. The AES crypto engine provides a simple interface for data and keys to easily integrate with the rest of the system. The design operates at 300 MHz in 90nm and delivers 128-bit blocks per 12 cycles (3.2 Gbps) with 70K gates. The optimized design for gate count is 30k and achieves a throughput of 1 Gbps. The block performs both encryption and decryption. The base design can be configured to run at lower clock speeds by loop unrolling (with more area). The design is amenable to be implemented using T-Boxes and pre-computed Round Key Memory for higher throughput.

Benefits:
Flexible enough to configure various data rates and sizes depending on the applications
Supports EBC, CBC and CTR modes of operation Provides simple interface for integration
Performs both encryption and decryption

Features

Compliant with FIPS 197 NIST publication

Supports OFB, CFB, CCM, CBC, CTR, and EBC modes

Supports 128, 192, and 256-bit keys

Encryption and Decryption using the same block

70K gates at 300 MHz in 90nm technology. (30K gates for area optimized)

3.2 Gbps performance for 128 bit Key length

Automatic Round Key generation per cycle

Silicon and FPGA Proven and is interoperated with IPSEC devices

Configurable to connect to APB or AHB or a MIPS style Co-Processor bus

Customizable to add a staging layer for key and data storage

Deliverables

Verilog RTL for the design

Testbench and Testcases to verify the configuration

Complete test suite that includes NIST Tests

Synthesis scripts

Documentation

Market Category

Communications, Consumer Electronics

Datasheet

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Bus Interface

AMBA AXIAMBA AHB

Protocols

AMBA 4.0 AHB
AMBA 4.0 AXI
DDR2
DDR3
PCI
PCIe
SPI-3
SPI-4.1
SPI-4.2
SPI-5

Gate Count

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QIP Rating

This IP is not yet QIP rated.

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