The Helion Fast Hash core family implements the NIST approved SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512 Secure Hash Algorithms to FIPS 180-3 and the legacy MD5 hash algorithm to RFC 1321. These are high performance IP cores that are available in single or multi-mode versions and have been designed specifically for use in Xilinx FPGA. The hash algorithms take as input a message of arbitrary length, process the message as a series of 512 or 1024 bit blocks, and produce as output a compressed representation of the message data in the form of a message digest, the length of which varies with hash algorithm. Applications for the hashing cores include implementations of the standard Keyed-Hash Message Authentication Code (HMAC) described in FIPS 198-1. They are commonly used in the IPsec and TLS/SSL protocols, as well as Digital Signature applications, where a hash function is required to ensure both data integrity and origin authentication.
Features
Implements one or more of SHA-1, SHA-224, SHA-256, SHA-384, SHA-512 & MD5 hash algorithms
Fast operation â€" one clock per hashing algorithm round
Performs automatic message length calculation and padding insertion
Optional user initialisation of IVs for efficient HMAC support
HMAC wrapper available for quick and easy implementation
Optional state unload/reload feature for handling fragmented messages
Highly optimised for use in Xilinx FPGA
Deliverables
Target specific netlist or fully synthesisable RTL
VHDL/Verilog simulation model and testbench with FIPS test vectors
Comprehensive User documentation
Example simulation scripts
Market Category
Automotive, Communications, Consumer Electronics, Data Processing, Industrial and Medical, Military/Civil Aerospace