High Speed Standard Cell Logic Library Multi-Channel 35nm, TSMC 28HPM HVT

Estimate your chip with this semiconductor IP

Synopsys

IP Name

Logic Library, High Speed, Multi-Channel 35nm, TSMC 28HPM HVT

Provider

Synopsys

Description

High Speed Standard Cell Logic Library Multi-Channel 35nm, TSMC 28HPM HVT

Categories

IP Catalog : Digital Core IP : Standard Cell Libraries : Density Optimized

IP Catalog : Digital Core IP : Standard Cell Libraries : Performance Optimized

IP Catalog : Digital Core IP : Standard Cell Libraries : Power Optimized

Portability

ASIC

Process Node

28nm/TSMC/HVT

Type

Hard IP

Maturity

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Overview

Synopsys' DesignWare® Logic Libraries portfolio includes the SiWare® Logic and ASAP Logic cell libraries. The SiWare Logic product line includes yield-optimized standard cells for a wide array of design applications from 65 nm to 28 nm process nodes with multiple threshold process variants. The ASAP Logic product line consists of metal programmable and standard cell libraries designed to meet the highest quality and performance standards for 180 nm to 90 nm process nodes.

Features

Maximum Performance - High-performance libraries for critical paths of GHz processors; Close timing in fewer iterations without sacrificing area or power

Minimum Power - Multi-channel libraries for 4X-5X static power reduction; Power Optimization Kits with over 200 cells; Support for low-power UPF and CPF EDA flows

Maximum Density - Patented NXT standard cell architectures for highest routing utilization; Multiple cell heights per process (~7, ~9 and ~12 track) for optimal tradeoffs; Hand-crafted layout for maximum density

High Yield - Design-for-manufacturing (DFM)-aware design and validation; Redundant contacts; Electro-migration (EM)-compliant at highest speeds

Comprehensive Solution - Electrically, physically and EDA-view aligned with DesignWare Embedded Memory products; Multi-VDD characterization with low voltage and overdrive PVTs

Multiple Libraries per Process Node

Multiple Cell Architectures for Optimal Power, Performance and Area

Optimized Cell Sets; Accurate Characterization

Availability of Process, Voltage and Temperature (PVT) Characterization Corners - Standard, overdrive and low voltage PVT clusters for timing and leakage; PVTs aligned with DesignWare Memory Compiler PVTs; Custom PVT development available

Silicon proven using Split Lots at Advanced Nodes - Correlated to EDA models; Low voltage testing to VDDMin

Deliverables

.lib

LEF

GDS

Verilog

CDL and other industry standard design views

Market Category

Communications, Consumer Electronics, Data Processing, Military/Civil Aerospace, Others

Datasheet

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Size

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QIP Rating

This IP is not yet QIP rated.

Customer Testimonial

"Developing the [USB] IP internally was never an option for us because it is not our core competency. Compared to other IP vendors we evaluated, Synopsys DesignWare USB 2.0 nanoPHY was 30% lower in area and up to 15% lower in power. It was one of the smallest PHYs we found. "

Laurent Sibony, Director of ASIC Designs
Sequans

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