Synopsys' DesignWare® Logic Libraries portfolio includes the SiWare® Logic and ASAP Logic cell libraries. The SiWare Logic product line includes yield-optimized standard cells for a wide array of design applications from 65 nm to 28 nm process nodes with multiple threshold process variants. The ASAP Logic product line consists of metal programmable and standard cell libraries designed to meet the highest quality and performance standards for 180 nm to 90 nm process nodes.
Category
Portability
Process Node
Type
Maturity
Market Category
QIP Rating
IP Catalog : Digital Core IP : Standard Cell Libraries : Density Optimized
IP Catalog : Digital Core IP : Standard Cell Libraries : Performance Optimized
IP Catalog : Digital Core IP : Standard Cell Libraries : Power Optimized
ASIC
55nm/GLOBALFOUNDRIES/LP
Hard IP
Please login or register to view this data
Communications Consumer Electronics Data Processing Military/Civil Aerospace Others
This IP is not yet QIP rated.

Synopsys delivers semiconductor design software, intellectual property (IP), design for manufac
The Case for Developing Custom Analog
The contents of this document are owned or controlled by S3 Group and are protected under applicab...
DOWNLOAD