The Mini-LVDS transmitter converts up to 64-bit CMOS data into 16-pairs of Mini-LVDS data stream that can support Single-Link transmission with up to SXGA+ resolution, or Dual-Link transmission with up to UXGA resolution. This IP is suitable for Flat Panel Display applications.
Process: IBM 65nm 1.0V/2.5V cmos10sf, support metal option (TBD)
Logic input: total 64-bit data inputs, clock trigger edge selectable
Mini-LVDS output: Single-Link or Dual-Link; 8-channel data + SP + clock for each link