Infineon's 16-bit C166Sv1 processor in a configurable subsystem featuring a rich set of standard peripherals

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Infineon's 16-bit C166Sv1 processor in a configurable subsystem featuring a rich set of standard peripherals

• IP Catalog : Digital Core IP : Microcontrollers : RISC
• IP Catalog : Digital Core IP : Subsystems : Platform IP

• Four-stage pipelined CPU with multiple register banks and single-cycle context switching
• C166 instruction-set compatible plus additional DSP instructions with optional MAC unit -- 16 * 16 multiply in 1 cycle with MAC unit or 5 cycles without MAC -- 32/16 division in 10 cycles
• On-Chip Debugging System (OCDS) with debug interface supporting hardware, software, and external breakpoints, and access to internal registers and memory through JTAG port
• Multiple high-bandwidth internal buses: XBus+, PDBus+, LM66, DPRAM plus External Bus Controller (EBC) supporting external bus and general purpose I/O ports
• Interrupt controller supports up to 112 interrupt nodes with separate vectors
• Peripheral Event Controller (PEC) supports interrupt-driven, single-cycle data transfer with optional channel linking
• Core Control Block (CCB) provides power/clock management for CPU and peripherals
• Synchronous and asynchronous serial communication interfaces
• General purpose timer

• RTL source for hardware synthesis and simulation
• Integration testbench
• Full documentation
• Automatic configuration and synthesis/simulation script generation