Infineon C166S V1 Core with four-stage pipelined CPU and optional MAC unit

IPextreme

Infineon C166S V1 Core with four-stage pipelined CPU and optional MAC unit

• IP Catalog : Digital Core IP : Microcontrollers : RISC
• IP Catalog : Digital Core IP : Subsystems : Platform IP

• Four-stage pipelined CPU with multiple register banks and single-cycle context switching
• Most instructions execute in 2 cycles
• Optional MAC unit
• 16 * 16 multiply in 1 cycle with MAC unit or 5 cycles without MAC; 32/16 division in 10 cycles
• Scalable interrupt controller supporting 12–112 interrupt nodes
• External Bus Controller that supports the Infineon XBus+ protocol and provides support for the off-chip external bus interface
• On-Chip Debugging System (OCDS) with debug interface supporting hardware, software, and external breakpoints, and access to internal registers and memory through JTAG port

• RTL source for hardware synthesis and simulation
• Integration testbench
• Full documentation
• Automatic configuration and synthesis/simulation script generation