The Infineon C166S synthesizable processor core is derived from the successful C166 microcontroller family and is fully instruction set compatible to run all your legacy code. It has been designed to meet the high performance requirements of real-time embedded control applications. The architecture of the C166S combines the benefits of both RISC and CISC (Reduced and Complex Instruction Set Computing). This well-balanced approach delivers the memory saving code density and fast context switching of CISC with the easy RISC instruction decode that enables fast clocking.
Four-stage pipelined CPU with multiple register banks and single-cycle context switching
Most instructions execute in 2 cycles
Optional MAC unit
16 * 16 multiply in 1 cycle with MAC unit or 5 cycles without MAC; 32/16 division in 10 cycles